[SI-LIST] Re: Layout Cross Section

Just to make sure I'm not misunderstood, I don't mean to imply that
folks shouldn't use their own field solvers to decide their approximate
geometries. =20

But, to show the complexity of building an accurate model, look at a
"simple" microstrip on FR4, and try to determine Z0.  There are several
variables:
1)  trace width on bottom of the trace
2)  trace width on top of trace
3)  thickness of trace
4)  thickness of plating
5)  shape of plating (might make the trace look like a mushroom)
6)  properties (Er & loss tangent, and as a function of frequency) of
fiberglass weave
7)  properties of epoxy
8)  resultant properties that trace "sees" - function of weave type, and
where the trace aligns on that weave
9)  properties of soldermask
10) thickness of soldermask above trace
11) thickness of soldermask beside the trace (and this changes,
depending on nearby geometries)
12) how does soldermask transition between 10 & 11?
13) properties of copper
and the list goes on...

For every one of these variables, there are not only nominal values, but
expected deviations due to process variations.  To accurately model the
complete problem you must build models representing all possible
instances you might encounter.  Your resultant Z0 will not be a single
value, but a range, depending on how each variable might behave.  Of
course, you'll find out that some variables don't matter, but that's
part of the exercise.

It might be more efficient to gather empirical data and determine the
proper trace width (and resultant expected Z0 variation) from that.  I
hope your board vendor is doing this.

Of course, field solvers (and why you would need more than 2D for this
problem, I don't know) will play an essential part in your stackup
decision and trace/spacing geometries, but they can only give you an
approximation, limited by your knowledge of the specifics of the
variables.

In short, I believe field solvers and empirical data should both play a
significant part in the design.

I think this is about as clear as I can make myself - I probably won't
spend any more energy with further rebuttals.

Jeff Loyer


-----Original Message-----
From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx]=20
Sent: Saturday, February 21, 2004 12:46 PM
To: David Hoover; Loyer, Jeff; cadpro2k@xxxxxxxxxx;
si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Layout Cross Section


I agree with what Dave has to say.  It is also pretty easy to get the
data
and solvers and do the work yourself.  The reason that stackup design by
a
fabrication shop has risk is the assumption being made it that impedance
is
the only parameter of importance and that is simply not so.  Interplane
capacitance and cross talk are equally important and those cannot be
accounted for by your fabricator.

I team with a fabricator to balance all of these things along with
manufacturability. That's the best approach.

Lee =20


> [Original Message]
> From: David Hoover <dhoovy@xxxxxxxxxxxxx>
> To: Loyer, Jeff <jeff.loyer@xxxxxxxxx>; <cadpro2k@xxxxxxxxxx>;
<si-list@xxxxxxxxxxxxx>
> Date: 2/20/2004 5:52:47 PM
> Subject: [SI-LIST] Re: Layout Cross Section
>
> Jeff,
>
> You'll find that the better fab shops in the US (at least) are already
> using at least 2D Field Solvers. Most of the laminate manufacturers
are
> already supplying Dk and Df values at various frequencies just for
these
> kinds of purposes. For years the fabricators have found a way to make
it
> work
> without this data. Now that the data is available and the simulation
tools
> are
> also available we (fabricators) are calculating with far more accuracy
than
> before. We also have the ability to do different environments far and
beyond
> standard Motorola MECL formulas. (Including mixed dielectrics)
>
> There may be a few smaller fab shops still around that use the
"empirical
> data" approach and are very good at it. I'm not knocking that. I did
it
for
> years.
> But approach them with a differential microstrip with no reference
plane
> below
> (infinite ground) and see what happens. The tools available to the
> fabricators
> have come along ways.....  Thanks to you design guys that allowed the
tools
> to break out of the design suite software.
>
> Regards,
>
> David Hoover
> Sr. Field Application Engineer
> Multilayer Technology, Inc.
>
> ----- Original Message -----=20
> From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
> To: <dhoovy@xxxxxxxxxxxxx>; <cadpro2k@xxxxxxxxxx>;
<si-list@xxxxxxxxxxxxx>
> Sent: Friday, February 20, 2004 12:47 PM
> Subject: RE: [SI-LIST] Re: Layout Cross Section
>
>
> I have to respectfully disagree with this method, a bit.  In some
> instances it is a very good thing to get definitive fab geometries,
> dielectric constants, and all the sometimes obscure data you must take
> into account to build an accurate model to determine the properties of
> your stackup.  But, in my personal experience, that's not a task to be
> taken lightly.  Unless you have a specific need to delve into the
> nitty-gritty, I would opt for relying on the fab vendor's empirical
data
> to determine stackup to achieve the right impedance, for instance.  Of
> course, this depends on the vendor's data collection method and their
> analysis, but they should have the data and experience.  If they
don't,
> and/or you opt to go through the exercise of precisely determining all
> the relevant factors yourself, be prepared for a lengthy study.
>
>
> Jeff Loyer
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of David Hoover
> Sent: Friday, February 20, 2004 6:28 AM
> To: cadpro2k@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Layout Cross Section
>
>
> The best thing to do is make sure you understand your fabricators true
> finished product
> parameters. The trapezoidal shape of the etched copper conductor makes
a
> huge difference
> in the calculated impedance results. (Hopefully your calculator has
that
> as
> an entry)
> Next, you need to use the effective relative permittivity (Er') of the
> material at the frequency
> that the TDR sees (based on the risetime of the TDR. Usually around 1
to
> 1.75 GHz
> nominally for FR4) You can't just use the bulk material values (around
> 4.5
> at 1 MHz).
> Those are fine for 2 sided because there is so many sheets of material
> stacked up.
> But multilayers have higher resin to glass ratios and end up with a
much
> lower Er'
> value.
>
> Each type of material is different, so ask your fabricator for a list
of
> Dk
> values
> at different frequencies to help you better understand the variables.
> Removing parameters
> and adjusting the variables to get the calculated result to match the
> measured is not the best
> thing to do. Trust me I KNOW! The fabricators have done it for years
and
> some may still
> be doing this. Ever hear the words "Empirical Data Adjustment"?  (It's
> like
> a mental slide rule)
>
> The 2D and 3D Field Solvers today have the ability to accurately
> calculate
> and solve the
> mystery. That coupled with entering the real values will produce
results
> so
> close that there
> is no need to adjust parameters to "tweak" the results.
>
> Of course if you only have a static equation calculator (like the MECL
> stuff) then I
> guess your stuck fidgeting with the numbers. : /
>
> David Hoover
> Sr. Field Application Engineer
> Multilayer Technology, Inc.
>
> ----- Original Message -----=20
> From: <Aubrey_Sparkman@xxxxxxxx>
> To: <cadpro2k@xxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Sent: Thursday, February 19, 2004 10:36 AM
> Subject: [SI-LIST] Re: Layout Cross Section
>
>
> > Uri, Mitch,
> > You don't need to mess with your material.dat file; adding a layer
of
> FR4
> > works.  Before you do your testing, delete your interconn.iml file;
> you
> want
> > to make sure Allegro re-computes the parasitics.  I opened a test
> board I
> > have, selected "DISPLAY/PARASITICS", and clicked on a trace on the
top
> layer
> > and got:
> > 57.113 ohms
> > 36.207 nH
> > 11.1 pF
> > 0.633954 nS
> >
> > I then removed the FR4 layer and did the "DISPLAY/PARASITICS" thing
> again:
> > 64.334 ohms
> > 36.2065 nH
> > 8.74793 pF
> > 0.562789 nS
> >
> > To me this says everything changed about the right amount in the
right
> > direction.
> >
> > Aubrey Sparkman
> > Enterprise Engineering Signal Integrity Team
> > Dell, Inc.
> > Aubrey_Sparkman@xxxxxxxx
> > (512) 723-3592
> >
> >
> > > -----Original Message-----
> > > From: si-list-bounce@xxxxxxxxxxxxx
> > > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Mitch S. Morey
> > > Sent: Thursday, February 19, 2004 10:48 AM
> > > To: si-list@xxxxxxxxxxxxx
> > > Subject: [SI-LIST] Re: Layout Cross Section
> > >
> > >
> > > Hi Uri,
> > >
> > > Before you get into material.dat file, and the parameters and
> > > what-not, I
> > > experimented with changing some variables in my stackup and
> > > the impedance
> > > DIDN'T change. I tried FR4 over top; conformal coat; etc; changed
> > > thicknesses; Dk and when I do DISPLAY/PARASITICS on my Clines
> nothing
> > > changes. Might be worth your time to experiment first.  :)
> > >
> > > Mitch
> > > >
> > > > Hi !
> > > > Thanks for all answer me Kim, Mitch ( nice joke :) and Jeff.
> > > > Do you know what parameters of soldermask ?
> > > > Now I know that possible edit material.dat and now I need
> > > to do this.
> > > > Uri
> > > >
> > > > -----Original Message-----
> > > > From: Jeff Seeger [mailto:jseeger@xxxxxxxxxxxxxx]
> > > > Sent: Wednesday, February 18, 2004 8:38 PM
> > > > To: si-list@xxxxxxxxxxxxx
> > > > Subject: [SI-LIST] Re: Layout Cross Section
> > > >
> > > >
> > > > Uri Chaplianka wrote:
> > > >>
> > > >> snip <
> > >
> > >
> > >
> > > -----------------------------------------
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