[SI-LIST] LDO Heat Dissipation with Vias

All,

We have a TI LDO (TI1963A-25KKT) in a KTT package (9.65mm x 10.67mm thermal 
pad), but we don't have the space on our (16 layer) board for the required 50mm 
x 50mm copper pours on the top and bottom.  We're hoping to use the internal 
GND planes to help dissipate the heat away from this component, and have placed 
some vias *nearby* the LDO pad for this purpose.

Wondering if placing vias right in the ground pad under a chip of this size is 
going to cause any issues with the soldering process?  Certainly the contact 
with the ground planes in our stack is improved if the heat can travel direct 
instead of only through the neighboring vias.

Any experience/insights would be appreciated.

Kind Regards,

Shawn

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