[SI-LIST] Re: LA probes

...or maybe..... you said it was a bi-dir bus. Bi-dir buses always have
the ability to be tri-stated, so maybe it's in a hi-impedance
state...and it has an internal pullup to 3.3v. when you probe with a
hi-Z probe it reads 3.3v, but when you probe with a 20K ohm probe it
splits up the 3.3v and only reads 2v.

just a guess, but couldn't resist (no pun intended).

Regards,
Jim Peterson
Honeywell

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Monday, July 30, 2007 3:41 AM
To: anand.srinivasan@xxxxxxxxxxxxx
Cc: olaney@xxxxxxxx; prajitsnair@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: LA probes

Anand, if a static logic high level is getting dragged down, then you=20
have some fundamental problem like a terminator enabled in the probe or=20
perhaps the FPGA input buffer that you do not intend or even a trace=20
short.  First find out if this is due to the LA or not.  If the problem=20
appears only with the LA connected then check your manuals to insure you

have:  a correctly selected and functioning probe head, that is set-up=20
properly.  If the problem appears without the LA connected, then you=20
likely have:

* Misprogrammed FPGA that has terminators enabled within the FPGA I/O
cells
* Bus contention
* A wiring problem

Steve

SRINIVASAN ANAND-B06739 wrote:
> I have mapped to CMOS logic family. The probe impedance is 20K. I am
> seeing a voltage of 2.0 V on a static pin on which I was expecting
3.3V.
>
>
> -----Original Message-----
> From: olaney@xxxxxxxx [mailto:olaney@xxxxxxxx]=3D20
> Sent: Monday, July 30, 2007 12:00 PM
> To: prajitsnair@xxxxxxxxx
> Cc: SRINIVASAN ANAND-B06739; si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: LA probes
>
> Does the logic analyzer allow you to specify the logic family
> parameters?
>  You might have the wrong setting, for instance PECL loading on a CMOS
> signal.
>
> Orin
>
> On Mon, 30 Jul 2007 15:19:39 +0900 "PRAJIT S  NAIR"
> <prajitsnair@xxxxxxxxx> writes:
>  =20
>> Dear Anand
>> It may be happening because of probe loading. Please check your
Probe=3D20
>> Capacitance, Frequency of Operation and also Load impedance.
>> =3D20
>> =3D20
>> Best Regards
>> Prajit
>> =3D20
>> =3D20
>> On 7/30/07, SRINIVASAN ANAND-B06739 <anand.srinivasan@xxxxxxxxxxxxx>
>> wrote:
>>    =20
>>> Content-Type: text/plain;
>>>        charset=3D3D"us-ascii"
>>> Content-Transfer-Encoding: quoted-printable Hi All, I have a=3D20
>>> problem. Given below is a topology that i have.=3D3D20
>>>
>>>
>>>
>>> =3D3D20
>>>
>>> =3D3D20
>>>
>>> I have a bidirectional bus which connects a FPGA to the CHIP. =
The=3D20
>>> distance between them is 2 inches. Now to probe this bus, i have
>>>      =20
>> the
>>    =20
>>> signals coming out to the right at a distance of about 6 =
inches.=3D20
>>>      =20
>> Note
>>    =20
>>> that i am using active probes to probe this interface and there
>>>      =20
>> are NO
>>    =20
>>> buffers on the line between the chip and LA probes. Now the
>>>      =20
>> problem is
>>    =20
>>> that when the LA is plugged in I find that the strength of the
>>>      =20
>> signals
>>    =20
>>> driven by the chip comes down from 3.3V to 2V. Without the LA
>>>      =20
>> plugged,
>>    =20
>>> the signal strength remains intact. Could anyone help me in=3D20
>>> understanding this? If a solution is possible to get around this,
>>>      =20
>> it
>>    =20
>>> will be great.
>>>
>>> =3D3D20
>>> Regards,
>>> Anand
>>>
>>> =3D3D20
>>>
>>> =3D3D20
>>>
>>>
>>>
>>>
>>> -- Binary/unsupported file stripped by Ecartis --
>>> -- Type: image/jpeg
>>> -- File: Outlook.jpg
>>> -- Desc: Outlook.jpg
>>>
>>>
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--=20
Steve Weir
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