[SI-LIST] Re: LA probes

Does the logic analyzer allow you to specify the logic family parameters?
 You might have the wrong setting, for instance PECL loading on a CMOS
signal.

Orin

On Mon, 30 Jul 2007 15:19:39 +0900 "PRAJIT S  NAIR"
<prajitsnair@xxxxxxxxx> writes:
> Dear Anand
> It may be happening because of probe loading. Please check your 
> Probe
> Capacitance, Frequency of Operation and also Load impedance.
> 
> 
> Best Regards
> Prajit
> 
> 
> On 7/30/07, SRINIVASAN ANAND-B06739 <anand.srinivasan@xxxxxxxxxxxxx> 
> wrote:
> >
> > Content-Type: text/plain;
> >        charset="us-ascii"
> > Content-Transfer-Encoding: quoted-printable
> > Hi All,
> > I have a problem. Given below is a topology that i have.=20
> >
> >
> >
> > =20
> >
> > =20
> >
> > I have a bidirectional bus which connects a FPGA to the CHIP. The
> > distance between them is 2 inches. Now to probe this bus, i have 
> the
> > signals coming out to the right at a distance of about 6 inches. 
> Note
> > that i am using active probes to probe this interface and there 
> are NO
> > buffers on the line between the chip and LA probes. Now the 
> problem is
> > that when the LA is plugged in I find that the strength of the 
> signals
> > driven by the chip comes down from 3.3V to 2V. Without the LA 
> plugged,
> > the signal strength remains intact. Could anyone help me in
> > understanding this? If a solution is possible to get around this, 
> it
> > will be great.
> >
> > =20
> > Regards,
> > Anand
> >
> > =20
> >
> > =20
> >
> >
> >
> >
> > -- Binary/unsupported file stripped by Ecartis --
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> >
> >
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