[SI-LIST] Re: Jitter transfer vs. accumulation

Craig,
I have sat on both side of the table and there are always two sides of a =
story.
I am speaking on my own perspective and not putting words in others =
mouth here.
If you follow some of the references cited in this thread, you will =
realized the jitter characteristics of the PLL are well understood and =
can be analyzed in simulations over process and conditions ahead of the =
actual silicon. I have seen both SPICE (albeit with a supercomputer by a =
Japanese vendor) or Matlab analysis done on it. DVT is only a validation =
of a process point in your simulation in a typical process (or whatever =
skew lot you happened to be doing).
But turn the table around I will ask how many of you just blindly put =
that ferrite/R/C filter down on the PLLVDD without considering what band =
does it work in and does it even match the PLL jitter band ? How many of =
you even know there is a bandwidth trade-off in the PLL in accumulated =
jitter noise in PLL ? One can demand infinite information from you =
vendor, rightfully so. But do you even know what to ask in the first =
place ?
Finally, even the architecture of the SERDES itself makes a big =
difference. If you recalled I made the same mistake at the beginning of =
the thread. It makes a big difference in PLL loop bandwidth trade off if =
you have to recover the clock at the Rx vs. you phase interpolate the =
incoming data with a Rx clock from the same source. Luckily (or =
un-luckily to the PCIe Gen II community) I re-read the spec again and =
realize the PCIe spec actually force both Tx PLL and Rx PLL to have a =
horrible bandwidth w.r.t. the jitter accumulation.
I am waiting to be proven wrong, but it seems the PCIe Gen II community =
ask HALF of a question, that is the jitter TRANSFER aspect of PLL and =
drew a conclusion completely biased towards that end.
What I have raised, and you now seems to also ask, is the SECOND HALF of =
the question, that is the jitter ACCUMULATION aspect of PLL and people =
may draw a different conclusion.
A healthy discussion is good, ignoring the problem is bad.

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Craig Twardy
Sent: Monday, March 26, 2007 8:15 AM
To: Istvan.Novak@xxxxxxx; Tang, George
Cc: Alfred P. Neves; weirsi@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Jitter transfer vs. accumulation


Istvan;

I support your request for (better) characterization of serdes'.
I spend a lot of time trying to get performance data for devices.=3D20
But this is necessary to determine if the design will work in
production.


I understand there are many serdes standards, but usually it is the=3D20
Same piece of silicon that meets all or most of the standards. If the
silicon
Is properly characterized once, then one can determine whether it will
comply
With any number of standards. Why does it have to be re-characterized 20
times?


Craig



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