[SI-LIST] Jitter Characterization on a Tester?
- From: "Jay Shenoy" <jshenoy@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 1 Oct 2002 22:30:51 -0700
Hi All,
This is something that a peculiar circumstance has forced us into thinking
about, and I
would like to tap into the collective wisdom of this list.
- What is industry standard practice for characterizing jitter in production
testing of
ICs? Particularly for those of you at semiconductor shops, what does your
company do?
- I am aware that Wavecrest sells into the ATE market Is it relatively common
practice to include something like this for testing complex devices?
- How about significantly less sophisticated methods of frequency counting?
- Has any of you run into jitter related test escapes?
We recently ran into *one lot* of NPU's (from a vendor who shall remain
unnamed, inspite
of un-stellar customer responsivemess) that exhibited a very high amount of
jitter from the
PLL going unstable at the frequency of operation. Somehow this escaped their
testing (we
dont know what that involves, due to said unresponsiveness), and neither the
vendor nor
their other customers ran into this lot, it would seem. (Perhaps some customers
used a lower
frequency of operation for this clock domain).
We are still in engineering mode, hence we zeroed in on this reasonably
quickly. But the question
of how to prevent such occurences in production mode is something that my
company is
scratching it's head about. Any tips?
Thanks
Jay
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