[SI-LIST] JEDEC DDR3 SODIMM trace length rules

hi
i am just reading the DDR3 SODIMM standard from JEDEC, No21C.
but i dont understand, where are these ADD/COMM/CONT/CLK trace lengths coming 
from???
is it just like that they designed something without too much rules, then they 
measured lengths and left them in a standard document?

for different card topologies (also standardised), they specify very tight 
ADD/COMM/CONT/CLK routing length rules, and all are different for the different 
topologies.
what DDR JESD79-3B timing parameters or controller programmable valid DLL 
values determine these lengths?
they say if someone wants to use different topology, then they have to simulate 
it. is there any specific (not general signal integrity) requirement what i 
have to be aware at simulation? (for example use lane-to-lane delays of n*dT 
where dT is the controller DLL granularity)

i have to design a board with 2 different dram-chip populate options, to 
support either total 2GByte with single-die or 4GByte with dual-die chips. 
basically the routing should be the same for them, with an exception that i 
need 2 clock diffpairs even for the singledie option too (BIOS enable?, or 
using PLL CLK driver/fanout on-board...). but the Jedec21C specifies different 
trace segmenth lengths for the appropriate topologies (raw card B and D), and 
they specify them very tightly (no overlap).
my colleague says, its not adviced to offspin from the JEDEC dictated trace 
lengths... 
what can happen if for example I use raw card-D topology, and on some product 
variant, we solder singledie chips? (processorboard with soldered memory, the 
controller is intel GS_45)

Istvan Nagy
CCT, UK


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