[SI-LIST] Re: Information regarding Stackup Design.

1/2 oz Cu is more amenable to manufacturing thin traces required for 
impedance control with signal to plane dielectric 5mils or less.

Unless you have a lot of links that are 6Gbps or faster, most of your 
energy is closer to 1GHz than 10GHz.

Steve.

V S wrote:
> I have used Power Islands in the signal layers to reduce the number of 
> layers. These power islands can usually not be the IO plane and can be 
> successfully used for processor core and other places  where it goes to few 
> isolated pins and not to the whole board. The traces should be short and 
> wide. 
>
> For impedance, I usually let the PCB vendor send me the details of the Er 
> assumptions at frequencies involved. I have however not worked at 10 GHz.
>
> http://referencedesigner.com
>
>
> Gurus,
>
>
> I would like to get your valuable feedback on the following:
>
> 1) Advantages/Disadvantages about using 1/2 Oz Cu for signal routing on the 
> inner layers. One issue that I can think of is the potential increase in DC 
> IR 
> drop if I plan to use the signal layers for carving out a power island.  Are 
> there any other issues that I need to be aware of before going down this path?
>
>
>
> 2) I have seen substrate vendors specifying two different Er/Df values for 
> two 
> different frequencies (1GHz, 10GHz). What is the current industry practice 
> about which Er value to use when coming up with the trace geometries to meet 
> impedance requirements? I was planning to use the Er value at high frequency 
> since the edge rates for my scenario are fast. Any suggestions from the group 
> are welcome.
>
>
>
> Thanks,
>
> Ravi.
>
>
>       
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