[SI-LIST] Re: Inductance of VRM

Larry,  a couple of items I would like to throw in are:

1) Even a linear regulator has this inductive appearance as a result of 
decreasing closed loop gain with frequency.
2) The VRM may rely on loop gain to attain a given output impedance.  In 
that case, it is necessary to transition the VRM output well above 0dB loop 
gain.  The caution here is that the VRM may well be on a +2 slope, and 
severe ringing in the response can result.

3) In an SMPS, the output filter is always an LC, yielding by themselves a 
tank circuit, ripe for oscillation.  It was very important in voltage mode 
converters to include enough damping resistance to prevent objectionable 
peaking.  With current mode control, the state-space averaged behavior 
approximates a current source, reducing to the inductive characteristic you 
described.  An easy experiment is to apply a waveform generator to a pair 
of diodes and an LC output filter, and then use a sweep generator to 
modulate the duty cycle.

Regards,

Steve.
At 09:59 AM 3/22/2004 -0800, Larry Smith wrote:
>Chris - Steve has given you a good explanation below for why a VRM appears 
>inductive to the PDS.  With a single pole roll off for the transfer 
>function of the VRM, the closed loop output impedance vs frequency goes up 
>at about 20 dB per decade, just like an inductor.
>
>There is another explanation that may be more satisfying from a circuits 
>standpoint.  A buck switching power supply basically connects an inductor 
>between some head voltage (i.e. 12V) and the output voltage (~1.5V).  We 
>know that the current through the inductor is governed by the equation V = 
>L di/dt, and will ramp up or down according to this formula.  The voltage 
>across the inductor may be 12 - 1.5 = 10.5V.  Soon, the VRM is delivering 
>more current than the load wants and the output voltage rises.  The 
>control loop of the VRM senses this and switches some FETs so that the 
>inductor is now connected between the output voltage and ground.  This 
>puts a reverse 1.5V across the inductor and the current ramps down until 
>it is no longer supplying the needs of the load.  An output capacitor 
>integrates the current from the inductor and provides a smooth output 
>voltage at the desired level.
>
>It is actually a little more complicated than this because there is a 
>"heartbeat" frequency for the VRM and the inductor is actually switched on 
>and off with a duty cycle such that the loop remains in regulation.  But 
>this should give you some further insight into why the output impedance of 
>a VRM is inductive.  It also gives you some insight into the maximum di/dt 
>that a VRM can deliver.  It is easy to calculate the minimum response time 
>for the VRM to deliver a current transient.  For a well designed VRM, the 
>inductor is sized so that the inductor's response time with the given 
>input and output voltages is nearly the bandwidth of the loop as 
>determined by the amplifier and loop compensation components.  As Steve 
>indicates, the bandwidth of the loop is usually about 1/5 of the heartbeat 
>frequency.  This is necessary to keep the feedback loop stable.
>
>In any case, the output impedance of the VRM is inductive.  The impedance 
>of the equivalent inductance of a well designed VRM crosses the target 
>impedance near the bandwidth frequency of the regulation loop.
>
>regards,
>Larry Smith
>Sun Microsystems
>
>steve weir wrote:
>>Chris, the closed loop transfer function gives the VRM its phase shift 
>>versus frequency.
>>The VRM typically has multiple poles.  One of the poles is to effect an 
>>integrator transfer function for very high DC gain, and another is either 
>>the open-loop transfer function of the error amplifier in a linear VRM, a 
>>single effective pole from a current mode SMPS, or two poles from the LC 
>>output filter in a voltage mode SMPS.  Most SMPS have operated in current 
>>mode rather than voltage mode for the past twenty three years or so.  The 
>>error amplifier does not have to be set-up this way, but this has proven 
>>very cheap and effective.
>>The feedback loop must close the gain at 0dB while there is still phase 
>>margin to 180 degrees to prevent oscillation.    A VRM usually approaches 
>>0 dB to within 5-10dB on a -2 slope, and then cuts back to a -1 slope to 
>>stably cross 0dB.  At some point beyond 0 dB the phase can rapidly fall 
>>away to 180 degrees or more.  This means that the impedance is on the 
>>complementary slope of +2, and then goes to +1 near 0dB where the phase 
>>will actually be more like 135 degrees than 90 degrees lagging as with a 
>>simple inductive characteristic.  Where the decoupling network needs to 
>>transition from the VRM depends on how much greater the VRM open loop 
>>impedance is than the system target impedance.
>>Many modern VRMs have bandwidths into the 100's of kHz, and some linear 
>>regulators even into the low MHz, particularly if they have to support 
>>the current generation of power thirsty processors.  In an SMPS, the 
>>switching frequency sets the upper limit on frequency response.  Clearly, 
>>the loop cannot effect average voltage changes in a single cycle.  If we 
>>apply Nyquist, we are limited in the best case to Fsw/2.  However, 
>>typically, the feedback loop closes at 1/5th the switching frequency or less.
>>Steve.
>>At 09:10 AM 3/22/2004 +0000, Chris Chalmers wrote:
>>
>>>Si List,
>>>
>>>Here's a question that has been burning my brain cells.
>>>
>>>The effective operating frequency for a Voltage Regulator
>>>module in the PDS is from DC to a few hundred hertz.  Then the
>>>bulk capacitors take over from there to 1 MHz.  The VRM becomes
>>>inductive above a few hundred hertz.  My question is, what makes
>>>the VRM look inductive?  Is it the package of the device that
>>>is so inductive at 1MHz that the impedance begins to go above the
>>>target system impedance or is it that the bandwidth of the error
>>>amplifier inside is only in the hundred of kilohertz.
>>>
>>>If it is the error amplifier then why don't they increase the
>>>bandwidth of it and reduce the inductance of the package to
>>>reduce the need for bulk capacitance.
>>>
>>>Also if it is just the inductance of the package, if you put a
>>>1MHz sine wave through it (from the die to the point of load
>>>would the 1MHz signal rise be slewed due to the inductance that
>>>much?
>>>
>>>Thanks in advance
>>>
>>>Chris
>>>
>>>
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