[SI-LIST] Re: Importance of Package Height
- From: John Barnes <jrbarnes@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 04 Mar 2002 08:28:58 -0500
Brent,
I put together a set of power-distribution guidelines for a previous
employer in May 2000, which included recommendations on choosing ceramic
bypass capacitors. I used a Hewlett-Packard network analyzer to measure
a bunch of the capacitors that we usually used on our cards, along with
ones from some sample kits we had in the lab. After each measurement I
had the network analyzer give me the best series-RLC fit to the data.
The summary below shows that the smaller SMT capacitors definitely have
lower ESL (on the average) than the large SMT capacitors, and all of
them are better than pin-through-hole ceramic capacitors. It is also a
lot easier to get a small capacitor close to the pins/balls of an
integrated circuit than a large capacitor, which helps reduce your loop
area and thus the overall inductance.
0603 0805 1206 1210 1808 1812
-------- -------- -------- -------- -------- --------
ESR (mohm) 20- 330 4- 620 38- 680 23- 73 220 67- 77
ESL (pH) 120- 380 160-1000 240-1500 160-1400 570 620-1400
-------- -------- -------- -------- -------- --------
C0G/NP0 ESR 160- 240 140 180- 680
C0G/NP0 ESL 150- 220 160 240
X7R ESR 27- 330 4- 620 38- 450 67- 69 220
X7R ESL 120- 280 190- 900 330-1500 440- 610 570
Z5U ESR 20- 93 35
Z5U ESR 190- 220 540
Y5U/Y5V ESR 20- 45 51- 69 60- 77 23- 72 67- 77
Y5U/Y5V ESL 190- 380 170-1000 440-1500 160-1400 620-1400
For comparison, radial ceramic capacitors measured 1-250 mohm ESR and
6100-11000pH ESL.
As a side comment, from my measurements the dielectric does not affect
ESR and ESL until you reach/exceed the SRF. The impedance of
C0G/NP0 capacitors then follows an inductive path, while X7R/Z5U/Y5U/Y5V
capacitors wallow around near the ESR for a while then start rising
slowly. This is probably good, because the lossy behavior will prevent
sharp resonances that could cause unwanted peaks in the
power-distribution network's impedance.
In some work that I did while writing my book, Electronic System Design:
Interference and Noise Control Techniques (Prentice-Hall, 1987), I found
that a fair model for the ESL of a ceramic capacitor is to treat it as a
non-ferrous blob of the same size. From theory, the partial inductance
of a non-ferrous strap of length=L, width=W, and thickness=T is:
ESL = (muv * L)/(2 * pi) *
[ ln(2 * L / (W + T)) +0.5 + (0.2235 * (W + T) / L) ] henries,
where muv is the permeability of vacuum or about 1.257 uH/meter.
So to a first approximation, when the thickness of the capacitor is
close to its width, the ESL will be roughly proportional to the
capacitor's length.
I also tried some experiments with putting the capacitors on edge
(plates vertical) versus their normal orientation (plates horizontal),
and found that it made a slight reduction in the ESL. The major
difference was that putting the capacitor on edge eliminated some wierd
high-frequency resonances that sometimes appeared in the normal
orientation. But the orientation is not really something that you can
control in automated mass production, so it was academic for us. If
this was a problem in a product, putting a lower value (by two or more
decades) ceramic capacitor in parallel with the troublesome capacitor
would be a much cheaper and easier solution.
John Barnes
dBi Corporation
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