[SI-LIST] Re: Importance of Package Height

Zhiping Yang Wrote:


> In the measurement method you discribed below, you actually
> measured the total loop inductance ( L_cap+L_vias+L_plane),
> is it right? There should are some ways to seperate the L_vias
> and L_plane from the L_totlal, since L_cap is more meaningful
> for some PDS tools.  It is always harder to define/extract partial
> inductance than loop inductance since loop indutance is always
> constant.
>
> >
Hi Zhiping:

Useful insight can be gained by expressing (and analyzing) the total PCB
mounted loop inductance by summation (as implied in your post):

   L_total = L_cap + L_vias + L_plane

Some of Larry Smith's writings indicate that the
inductance of mounting pad and via ( L_vias) which are geometry
dependendent range from 50 pH to 3000 pH, and that L_plane ranges from
50 pH to 1000 pH (depending on PCB dielectric thickness and capacitor
location).

Two series resonances  can emerge:

f0_self = 1/(2pi*sqrt(C * L_cap))

and

f0_mounted = 1/(2pi*sqrt(L_total * C ))

Where, f0_self and f0_mounted represent the ( un-monuted ) self series
resonant and PCB mounted series resonant frequencies of a ceramic capacitor
( of value C ) respectively.

Larry has earlier explained that it is easier first measuring the resonant
frequency then determining ESL. Let us solve for each inductance:

 L_cap = 1/ [C * (2 * pi * f0_self)^2 ]


 L_total = 1/ [C * (2 * pi * f0_mounted)^2 ]


Since L_total is larger than L_cap, then f0_mounted
should be smaller than f0_self .

Best Regards,

Abe Riazi
ServerWorks













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