[SI-LIST] Re: Impedance control with split ground planes

Balaji,

You may want to look into the possibility of making the stripline layers 
asymetrical: closer to
VCC on top and closer to GND on the bottom.  With blind vias you should 
be able to reach
down at least 10-12 mils, and dependent on the narrowest line your 
vendor can make, you could
use a trace-to-plane dielectric thickness of about 3 mils.  This will 
reduce (but not eliminate)
the impact of voids on the surface planes.

Regards,
Istvan


steve weir wrote:

>Balaji,   I don't think there are any simple fixes.  About the only 
>think you have going for you is that SDR 133 is pretty tolerant.  My 
>best recommendation is to start with the basics:  Propose a strategy 
>and test feasibility.  If it is feasible then work the details.  If 
>not, iterate using a different strategy.  I know no other reliable 
>way to design.  From your questions, it sounds like you may have 
>elected an implementation before determining overall feasibility.  If 
>so, it is time to back-up and see where you stand.  If you are lucky 
>then the strategy is feasible with some effort and/or changes.
>
>Good luck.
>
>Steve.
>At 12:52 AM 4/20/2006, Balaji S wrote:
>  
>
>>Hi Steve,
>>A small correction. My high speed signals are routed on S2 ( and not on
>>S1. typo).. Still is the design so flawed??
>>
>>Since due to microvias (aspect ratio 1:1) and cost constraint, we had to
>>go 4 that stack-up.
>>
>>Any suggestions for improvement will definitely be welcome..
>>
>>Regards
>>Balaji S
>>
>>
>>
>>steve weir <weirsi@xxxxxxxxxx>
>>Sent by: si-list-bounce@xxxxxxxxxxxxx
>>04/19/2006 07:30 PM
>>Please respond to
>>weirsi@xxxxxxxxxx
>>
>>
>>To
>>subramanian1683@xxxxxxxxx, si-list@xxxxxxxxxxxxx
>>cc
>>
>>Subject
>>[SI-LIST] Re: Impedance control with split ground planes
>>
>>
>>
>>
>>
>>
>>Subbu, it means the design is severely flawed.
>>
>>Steve.
>>At 06:44 AM 4/19/2006, Subramanian R wrote:
>>    
>>
>>>Hi Steve,
>>>Balaji, that dog won't hunt.
>>>
>>>Sorry, i didn't get u. wht was ur meaning??
>>>
>>>Regards
>>>Subbu
>>>
>>>On 4/18/06, steve weir <weirsi@xxxxxxxxxx> wrote:
>>>      
>>>
>>>>Balaji, that dog won't hunt.
>>>>
>>>>
>>>>Steve.
>>>>At 07:48 AM 4/18/2006, Balaji S wrote:
>>>>        
>>>>
>>>>>Hello All,
>>>>>I have a couple of queries:
>>>>>I have a stack-up as given below
>>>>>
>>>>>--------TOP
>>>>>--------S1
>>>>>--------VCC
>>>>>--------GND
>>>>>--------S2
>>>>>--------BOTTOM
>>>>>
>>>>>All high speed signals (SDRAM - 133MHz) are routed on S1.I have
>>>>>          
>>>>>
>>copper
>>    
>>
>>>>>pour on TOP and
>>>>>BOTTOM layers. The component density is High on both the outer
>>>>>          
>>>>>
>>layers,
>>    
>>
>>>>>hence a solid plane is not obtained.
>>>>>
>>>>>1. For controlled impedance calculations, do i consider the traces on
>>>>>          
>>>>>
>>S2
>>    
>>
>>>>>as striplines or Micro-strip lines?
>>>>>2. Our Fabricator told us that, when doing the impedance measurement
>>>>>          
>>>>>
>>on
>>    
>>
>>>>>coupons, he will
>>>>>   be considering GND and BOTTOM layers as solid planes. Will not
>>>>>          
>>>>>
>>the
>>    
>>
>>>>>result be different in the actual board,
>>>>>   since the Copper on BOTTOM layer is not completely solid?
>>>>>
>>>>>Thank you
>>>>>
>>>>>With Regards
>>>>>Balaji S
>>>>>
>>>>>          
>>>>>

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