[SI-LIST] Re: Impedance control with split ground planes

Hi Steve,
A small correction. My high speed signals are routed on S2 ( and not on 
S1. typo).. Still is the design so flawed??

Since due to microvias (aspect ratio 1:1) and cost constraint, we had to 
go 4 that stack-up.

Any suggestions for improvement will definitely be welcome..

Regards
Balaji S



steve weir <weirsi@xxxxxxxxxx> 
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04/19/2006 07:30 PM
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[SI-LIST] Re: Impedance control with split ground planes






Subbu, it means the design is severely flawed.

Steve.
At 06:44 AM 4/19/2006, Subramanian R wrote:
>Hi Steve,
>Balaji, that dog won't hunt.
>
>Sorry, i didn't get u. wht was ur meaning??
>
>Regards
>Subbu
>
>On 4/18/06, steve weir <weirsi@xxxxxxxxxx> wrote:
> >
> > Balaji, that dog won't hunt.
> >
> >
> > Steve.
> > At 07:48 AM 4/18/2006, Balaji S wrote:
> > >Hello All,
> > >I have a couple of queries:
> > >I have a stack-up as given below
> > >
> > >--------TOP
> > >--------S1
> > >--------VCC
> > >--------GND
> > >--------S2
> > >--------BOTTOM
> > >
> > >All high speed signals (SDRAM - 133MHz) are routed on S1.I have 
copper
> > >pour on TOP and
> > >BOTTOM layers. The component density is High on both the outer 
layers,
> > >hence a solid plane is not obtained.
> > >
> > >1. For controlled impedance calculations, do i consider the traces on 
S2
> > >as striplines or Micro-strip lines?
> > >2. Our Fabricator told us that, when doing the impedance measurement 
on
> > >coupons, he will
> > >    be considering GND and BOTTOM layers as solid planes. Will not 
the
> > >result be different in the actual board,
> > >    since the Copper on BOTTOM layer is not completely solid?
> > >
> > >Thank you
> > >
> > >With Regards
> > >Balaji S
> > >
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