[SI-LIST] Re: Impact of gap on stripline trace

Thanks for the responses.  You all have provided excellent information
for me to digest.

In the specific case that I presented, the gap occurs inside a package.
Thus, the features are quite small, including the gap spacing (~50um, or
2mils).  I think that that fact will mitigate deleterious effects.

Thanks again,

Frank

-----Original Message-----
From: bdempsey85@xxxxxxxxxxx [mailto:bdempsey85@xxxxxxxxxxx]=20
Sent: Wednesday, September 24, 2003 4:50 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Impact of gap on stripline trace

All,

Be sure to check the articles written by Doug Smith (a regular
contributor to=20
this list).  His articles on this subject are excellent reading.

A link to one in the series on the effects of splits can be read here:
http://emcesd.com/tt2002/tt120102.htm

Regards,
Bill
> Several years ago I built a test board similar to Frank's example.
There
> was a line on one side and a 0.100" gap between two different ground
planes
> on the other.  I built it so that I could place shorts between the two
> ground planes at various distances from the signal trace.  With no
short
> there was a large inductive spike as the signal passed over the gap as
> viewed on a TDR.  As I moved a short or cap closer and closer to the
trace
> the inductive spike both lowered in amplitude and shortened in time.
> Finally, when the short was right below the trace there was a minimum
> discontinuity on the TDR trace from the gap.  If I had widened the
short the
> discontinuity likely would have disappeared.
> Lesson learned, as long as you have a short return path for the ground
> currents you should not have significant impact on your signal.  If
the
> return path is long then you will see an significant impact.  If the
planes
> couple to each other the amount of coupling between the two planes
will
> dictate the discontinuity seen by the signal.
>=20
> Tom Dagostino
> Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
> 2926 SE Yamhill St.                Device Modeling Division
> Portland, OR 97214                 13610 SW Harness Lane
>                                    Beaverton, OR 97008
> http://www.teraspeed.com           503-430-1065=20
> tom@xxxxxxxxxxxxx=20
>=20
>=20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Loyer, Jeff
> Sent: Wednesday, September 24, 2003 3:01 PM
> To: fdunlap@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Cc: Loyer, Jeff
> Subject: [SI-LIST] Re: Impact of gap on stripline trace
>=20
>=20
> Hi Frank,
> My answer to your questions is conjecture based on my understanding of
=3D
> the physics, and on some experimentation done for a scenario not
exactly =3D
> like yours, but with some similarities.
>=20
> What is the impact of the gap?
> I think there are at least 3 issues here:
>=20
> 1) The path the return current must take as it transitions from:
>    a) 2 ground planes to=3D20
>    b) 1 ground plane plus 1 power plane to
>    c) 2 ground planes again
> I believe the inter-plane capacitance between the ground and power =3D
> planes will play the most significant role in determining the impact
to =3D
> Signal Integrity and EMI.  If the spacing between the plane below the
=3D
> trace and the one above the trace is small enough that there is a lot
of =3D
> inter-plane capacitance, AND the gap is small, I would expect
negligible =3D
> impact.  The return current will find an adequate path between the =3D
> different reference planes through the plane capacitance.  I would =3D
> expect this to be the case for typical stripline topologies, with =3D
> 15-20mils separating the planes.
> If the spacing between the top and bottom planes is large and the
plane =3D
> capacitances are small, the return current will find a substantial =3D
> discontinuity at the gap, causing signal integrity and EMI problems.
> It's also possible that the entire length the trace spends traversing
=3D
> under the power plane is insignificant, relative to the risetime
(though =3D
> it doesn't sound like this is the case in your scenario).
> I've pasted a synopsis of previous work concerning an issue similar to
=3D
> this (return path with various reference planes) below, under the
solid =3D
> line.
> I don't know how effective capacitors between the planes ("stitching"
=3D
> caps) would be.  For short risetimes, the effects of caps is
diminished =3D
> by their associated parasitics.  I would rather rely on inter-plane =
=3D
> capacitance.
>=20
> 2) The discontinuity of the gap itself.
> I would typically assume this is insignificant, since the gap will =3D
> probably be about 10mils, and that's only significant (using
risetime/6 =3D
> rule-of-thumb and 160pS/in Tp) for a risetime of less than ~10ps.
>=20
> 3) Another exotic effect - the gap becomes a waveguide
> I have heard of traces passing over a gap having substantial amounts
of =3D
> energy propagating along the gap, causing much more significant =3D
> crosstalk between adjacent traces than would be present without the
gap. =3D
>  I believe the information I saw was for microstrip; I don't know how
=3D
> much difference your scenario would be.  I don't have any details I
can =3D
> share about this - perhaps someone else has seen publications
describing =3D
> the effect?
>=20
> ________________________________
>=20
> I found that, when TDR'ing a stripline trace that was referenced to
both =3D
> power and ground, I got the same impedance whether decoupling caps
were =3D
> populated or not. Actually, instead of a cap, I physically shorted
power =3D
> and ground pins together at the launch point to keep even the
parasitics =3D
> of a capacitor out of the equation.  What I found was that, for the =
=3D
> stackup (5mil
> trace 7 mils above ground and 7 mils below Vcc), I saw no substantial
=3D
> difference, regardless of whether I measured:
> (1) with the probe referenced to GND,
> (2) referenced to VCC, and=3D20

> (3) with GND and VCC shorted together (at the launch).  =3D20
>=20
> Also, TDR'ing between the two planes shows a dead short.
>=20
> The risetime was ~50pS (a TEK TDR), and I even slowed the risetime
down =3D
> to 400pS, no change.  I'm pretty sure rise-time is not a factor.
> =3D20
> FURTHER INVESTIGATION: I wondered if, by definition of this
symmetrical =3D
> stripline, there isn't enough capacitance between the planes that the
=3D
> return current has a low impedance path to the reference plane.  I.E.,
=3D
> TDR'ing between the 2 planes shows a dead short - no need for external
=3D
> caps (or a shorting bar, in my case).
>=20
> This worked until I thought of the case of asymmetrical stripline - =
=3D
> would the impedance measured depend on which plane you were referenced
=3D
> to?  So, I built myself some crude asymmetric stripline (using a TDR =
=3D
> characterization board from TEK as a starting point).
>=20
> I took a microstrip trace (20 mils above ground plane) and added a
layer =3D
> of Kapton tape (2.5mils thick) over it, with a
> sheet of copper over that.  This turned the microstrip into a
stripline, =3D
> with the 2nd plane floating.  I TDR'ed the trace relative to Gnd, then
=3D
> relative to the floating plane, and with the planes shorted together
at =3D
> the source (again, relative to Gnd and the floating plane).
>=20
> I then added another layer of Kapton tape between the trace and the =
=3D
> floating plane, and repeated the measurements.
>=20
> I did this until I had 8 layers of Kapton tape between the trace and
the =3D
> floating plane.
>=20
> Granted, this was a pretty crude experiment and there were clearly
some =3D
> measurement errors, but some things were pretty obvious.
>=20
> Findings:
> 1) Regardless of the Kapton thickness, the lower impedance measured =
=3D
> (referenced to Gnd or the floating plane) was approximately the same
as =3D
> that as when the planes were shorted together.
>=20
> 2) With thin dielectrics (in the range that we typically use, <
7mils), =3D
> the impedance was approximately the same regardless of which plane was
=3D
> used as a reference, and whether they were shorted together at the =3D
> source.
>=20
> Conclusions:
> 1) When TDR'ing stripline, it probably won't matter which plane we use
=3D
> as reference.  If in doubt, I would TDR relative to whichever plane
was =3D
> closest to the trace.  If still not convinced, I would short the 2 =3D
> planes together at the source.
>=20
> 2) I would ensure that, when using stripline with both power and
ground =3D
> planes, the trace is closer to ground than power.  This is assuming
the =3D
> signal is routed relative to ground elsewhere.
>=20
> 3) I believe that a correct model for what I'm seeing is - it's the =
=3D
> parallel combination of Trace-to-Plane1, Trace-to-Plane1, and =3D
> Plane-to-Plane impedances that makes up the final impedance for a
trace, =3D
> relative to either Plane1 or Plane2.
>=20
> -----Original Message-----
> From: Frank Dunlap [mailto:fdunlap@xxxxxxxxxxxxxxxxx]
> Sent: Friday, September 19, 2003 6:46 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Impact of gap on stripline trace
>=20
>=20
> Consider a stripline signal trace that passes over a gap between a GND
> plane and an I/O PWR plane. The stripline is covered above by a GND
> plane.
> =3D20
> What is the impact of the gap?  Is it totally unacceptable for the
trace
> to cross this gap (there is a continuous GND plane on the other side
of
> the signal trace), or are there "speeds (edge rates)" for which the
gap
> may be okay?  If there are some "speeds" for which it is okay, how
does
> one determine those acceptable speeds?
> =3D20
> Does scale matter? In other words, if the gap is not acceptable for
> feature sizes common in a PCB, might the gap be acceptable at the
scale
> of feature sizes common inside high-speed IC packages?
> =3D20
> Regards,
> =3D20
> Frank
> =3D20
> -----------|  |-----------
>            |  |
>            |  |
>            |  |
>  GND       |  |  I/O PWR
>            |  |
> ------------------------------
>           SIGNAL TRACE
> ------------------------------
>            |  |
>            |  |
>            |  |
>            |  |
>            |  |
> -----------|  |-----------
> =3D20
> =3D20

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