[SI-LIST] Re: IBIS model doubt

Hi all,
Please see the Q&A mail thread I had with Arpad, related to IBIS models.
May be helpful to someone in future.
Regards,
Canes



________________________________
From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
To: Canes Venatici <starsilic@xxxxxxxxx>
Sent: Thursday, 20 November, 2008 11:40:36 AM
Subject: RE: [SI-LIST] Re: IBIS model doubt

 
Canes,
 
The general rule is that R_fixture should be close to
the impedance of the T-line that the buffer is designed
to drive.  However, V_fixture has an effect also on
the accuracy.  You can see a few waveforms in one of
my presentations:
 
http://www.vhdl.org/pub/ibis/summits/sep01/muranyi1.pdf
 
The conclusions don't say this, but looking at the
waveforms carefully, it seems that selecting V_fixture
values so that the signal and its termination in the
simulation is between the two V_fixture values usually
gives better results.
 
A solution to this problem could be the usage of more
than two waveform per output transistor, as shown in 
the second part of this presentation (pg. 14 and on):
 http://www.vhdl..org/pub/ibis/summits/jun03b/muranyi1.pdf 
 
 
But not too many simulators support more than four
V-t curves per buffer.
 
I hope this helps.
 
Arpad
=========================================================


________________________________





________________________________
From: Canes Venatici <starsilic@xxxxxxxxx>
To: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
Sent: Friday, 7 November, 2008 10:16:05 AM
Subject: Re: [SI-LIST] Re: IBIS model doubt


Thanks Arpad for your replies..

My simple question is does/how the accuracy of IBIS models
depends upon r_fixture/v_fixture values?

In otherway how can we select these values for a particular interface?

For e.g you were saying for DDR2 interface it will be an accurate model to 
connect vfixture to vdd/2
if similar termination is provided outside also. Does it mean the model would 
be accurate
if the board interface (for. e.g termination values, vref, rtermination) 
parameters are incorporated into fixture
values?

Please explain.

Regards,
Canes



________________________________
From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
To: Canes Venatici <starsilic@xxxxxxxxx>
Sent: Wednesday, 5 November, 2008 11:51:31 AM
Subject: RE: [SI-LIST] Re: IBIS model doubt

 
Canes,
 
No one knows what exactly the algorithms are in the
tools you mentioned, because the EDA vendors are not
making it public.  However, if you looked at the
waveforms in that presentation you will see a close
match between my VHDL-AMS implementation and HSPICE
(even in the area where they are not matching the
SPICE transistor model's waveforms) which could
mean that the algorithms may be the same or similar.
 
I am not sure what "cancellation" you are talking
about, but after the V-t tables have been converted
to K-t tables, there is no more need for the fixture
values.  The K-t tables are triggered at an event
(the stimulus going high or low) and the K-t tables
simply multiply the I-V tables with respect to time.
That's all there is to it...
 
Arpad
======================================================


________________________________
From: Canes Venatici [mailto:starsilic@xxxxxxxxx] 
Sent: Wednesday, October 29, 2008 7:01 AM
To: Muranyi, Arpad
Subject: Re: [SI-LIST] Re: IBIS model doubt


Arpad,
I feel I am slightly unclear with the fixture. Can I say, the values 
of Kpd(t) and Kpu(t)
will be independent of fixture values? The reason for this question is, in 
that case (yes) the 
fixture values will be effectively canceled by the intrepreter..
 
Combined with V-I, V-T and Kpx(t) the waveforms can be generated (by the 
intrepreter) 
which will model the IO close to spice accuracy. Am I right? 
 
Do you have any documents on how IBIS model is intrepreted (how 
algorithms intreprets various keywords) by 
intrepreters (HSPICE/hyperlynx)? 
 
Thanks and Regards,
Canes

________________________________

From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
To: Canes Venatici <starsilic@xxxxxxxxx>
Sent: Friday, 24 October, 2008 11:16:51 PM
Subject: RE: [SI-LIST] Re: IBIS model doubt

 
Canes,
 
1)  I would suggest that you look at the following presentation
to understand the reason for V_fixture and R_fixture:
 
http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf
 
Pg. 5 shows you the basic algorithm for an IBIS buffer model using
two rising and two falling waveforms.  If you had no V_fixture and 
R_fixture, you wouldn't' be able to calculate the output current 
with respect to time for describing the transient behavior (i..e.
the switching characteristics) of a buffer.The I-V curves alone
would only tell you what the buffer does when it is fully on high
or low, but they don;t tell you how to get there when it switches
high-to-low or low-to-high.  This is what the V-t curves help us
to figure out based on the equations shown on pg. 5.
 
2)  This is for generating the correct waveforms when the buffer
is switching.  The timing aspects are quite different from the
V_fixture and R_fixture numbers.  The other IBIS parameters, like
Rload, Vload, Cload, Vmeas are telling the tool how to measure
timing on the waveforms which were obtained in the simulation.
These parameters do not get used in the buffer's algorithms
for waveform generation, these are only used for using the
correct loading conditions to get a time point where the Tco
was evaluated for the buffer, and to start the timing measurement
from that point to where the waveform crosses the thresholds
at the receiver.
 
I hope this will help you to understand these parameters.
 
Arpad
=====================================================================


________________________________
From: Canes Venatici [mailto:starsilic@xxxxxxxxx] 
Sent: Thursday, October 23, 2008 8:10 AM
To: Muranyi, Arpad
Subject: Re: [SI-LIST] Re: IBIS model doubt


Arpad,
Thanks for your reply. For the time-being I am replying to you only to 
avoid huge number of "out-of-office" replies.
I will put across the threads into si-list at the end of our discussion. I 
have seen your IBIS class_2003 documents/
videos and trying to get a clear-cut understanding of IBIS models. Even I have 
sent a mail to your intel address 
and it got bounced back. Fortunately you replied and I am able to get your 
great help.

Please see the inscribed queries to make sure the right back-ground is set for 
my questions.

________________________________

From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Wednesday, 22 October, 2008 10:47:19 PM
Subject: [SI-LIST] Re: IBIS model doubt

1) The main reason for using the fixtures is to guarantee the maximun timing 
numbers 
mentioned on the data-sheet. This number will be reflected in the model if 
we use the 
same fixtures (as mentioned in data-sheet) while creating the IBIS. We 
can create IBIS 
at 0pF/0ohms/0v (fixtures) also but this may not give the worst case timing 
numbers as 
reported in the data-sheet. 
Is my understanding right?

2) If I use the fixtures while creating the IBIS models, the V-T curves may 
represent the
worst case numbers directly. Any other loading (while SPICE simulating IBIS + 
interface) may 
give numbers worse than worst case numbers mentioned in IBIS. 
Under this conditions will it be correctly representing the system?

3) If I do a simulation (for calculating delay/SI effects) with SPICE using 
the IBIS model + external interface, 
the spice-engine will use only V-I tables (which was not using any loads 
while getting created) and not
ramp data/rising/falling waveform.
Am I correct?

4) If point.3 is correct, why the V-T tables are required? 
If 'not correct' how the spice engine (while SPICE simulating IBIS + 
interface) may remove the 
fixture values and extract the timing data from IBIS so that only external 
interfacing effects 
on timing can be simulated?
---

Rest assured that a model generated under a specific
set of conditions will work reasonably well under other
conditions, but even if you have concerns about that,
the IBIS specification does have provisions for providing
V-t tables, for example at multiple sets of V_fixture 
and R_fixture conditions.  And if this is still not
enough, you can always make multiple IBIS models and
use the [Model Selector] keyword to allow the user to
switch between them.

But you cannot make a (behavioral) model without any load.
How would you obtain Vmeas, for example?  Or how would the
internal algorithm of an IBIS tool determine what the
output current was when the V-t curves were generated if
there was no V_fixture and R_fixture connected to the
output?

---
Canes: 
If I switch an unloaded IO (Cload = 0pF) which will have some intrinsic 
parasitic load 
(factored in C_Comp) I can still get V-T curve. For Vmeas, I can specify as
per the standard (for e.g in LVCMOS I will say V(typ/min/max)/2:  in SSTL 
anyway its
there in receiver spec vin(ach/l)).

In otherway:
I have got an IBIS model for an IO generated with v_fixture and r_fixture. Now, 
if I use this in my spice deck with external interface (terminations) I am 
afraid I am
using two terminations (one is from fixture and other from external termination 
I am
adding to the IBIS model in the spice deck). If the spice engine uses only V-I 
curves
while intrepreting IBIS, double counting may not occur.. If so why V-T curves 
are needed?

Please clarify me if I am completely misunderstood.
---
I hope this helps to clarify your concern.

Arpad
============================================================ 

Regards,
Canes


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Canes Venatici
Sent: Friday, October 17, 2008 12:52 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS model doubt

Hi all,
I haveA some doubts regarding the usage of IBIS models.
In the IBIS model,
1. Ramp measurement is done with a default value of 50ohms (R_load)A
connected to vref.
2. Also Rising/Falling waveformsA can beA simulated/measured with
R_/L_/C_fixture/V_fixture.
3. Cref and RrefA  for specifying the way delay was measured by the
manufacturer.

With the above informationA incorporated in the IBIS file, if used for
simulating
will it be correctly representing the I/O?
For e.g. with R_/L_/C_fixture/V_fixture/R_load effects included in the
waveform data, if I make 
some externalA terminations, it is in addition to the R_fixture/R_load
and may not correctly represent the system.

Instead, whyA don't we have only the un-loaded I/O bufferA modeled in
the IBIS so that
the designer who is using IBIS can put appropriate interface and do the
simulations.

Regards,
Canes


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Canes,

All of those parameters you mention are informational,
that is, they do not directly influence or describe the
behavior of the model.  They describe at what condition
the data was generated, or at what conditions certain
timing parameters were obtained.
---
Canes: 


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