[SI-LIST] Re: IBIS model Tr accuracy
- From: "Lynne D. Green" <lgreen22@xxxxxxxxxxxxxx>
- To: <Aubrey_Sparkman@xxxxxxxx>, <james.f.peterson@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 19 Oct 2005 10:10:25 -0700
Hello, Aubrey,
I found your "expectation" very educational. IBIS explicitly states that
all buffer data are for "bare" buffers, without package or other PDS
effects.
There is much effort in the IBIS community to address PDS effects. BIRD 95
has captured the current state of affairs.
Best regards,
Lynne
"IBIS training when you need it, where you need it."
Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@xxxxxxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Aubrey_Sparkman@xxxxxxxx
Sent: Wednesday, October 19, 2005 8:53 AM
To: james.f.peterson@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: IBIS model Tr accuracy
OK, disclaimer up front, one of the reasons I almost didn't respond to this
is because I don't consider myself to be an IBIS expert.
But to support your analysis, many IC suppliers know that supply sag due to
package PDS will slow down the buffer switching speed. As a user of IBIS
models, I expect that slowdown to be modeled in the "min" set of curves as
the weak buffer corner case along with temperature effects and minimum
supply voltage. The only, very minor, quibble I have is with your statement
"54AC245 is perhaps an exaggerated example." Older technologies have a
bigger difference between min and max corners.
PCI-X buffers, for instance, are allowed to have a wide switching speed
range, on the order of 0.36nS to 1.8nS for Tr and Tf. And I've seen many
models (and components) with fall times that were faster than the rise
times.
Did your IBIS model include min, max, and typ curves? Due to the large
variation in quality of the models I've acquired, I have gotten a wide range
of correlation to lab measurements (from None to excellent).
Aubrey Sparkman=20
Enterprise Engineering Signal Integrity Team Dell, Inc.=20
Aubrey_Sparkman@xxxxxxxx=20
(512) 723-3592
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Peterson, James F (FL51)
Sent: Wednesday, October 19, 2005 7:48 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS model Tr accuracy
Dear IBIS experts,
This question is related to the accuracy of the IBIS model's VT curves (or
the dv/dt #s).
We had noticed in the lab that our measured Tr and Tf were a lot slower than
what the IBIS model was stating, so we decided to take a closer look. The
part was a 54AC245.
=20
(You'll see below that Teraspeed was kind enough to make a version of the
model with the other 7 outputs toggling so that we could see the loaded
effect. our lab loading wasn't exactly the same, nor were our measurements
as accurate as Teraspeed's, so we have to keep the comparison general and
relative.)
note that all Tr and Tf measurements were made at 20%-80%...
IBIS model (a measured model from Teraspeed) (w/ other 7 outputs not
toggling) Tr=3D0.9ns Tf=3D0.6ns
(w/ other 7 outputs toggling) Tr=3D2.4ns Tf=3D1.0ns
Honeywell Lab measurement
(w/ other 7 outputs not loaded) Tr=3D1.4ns Tf=3D1.2ns
(w/ other 7 outputs loaded) Tr=3D2.5ns Tf=3D1.6ns=20
The take away message is that loading down other buffers will slow down the
Tr and Tf of the critical net you are analyzing. How much? Well it seems to
depend on how well your device delivers current to its buffers (AKA your
PDS). A 54AC245 is perhaps an exaggerated example, because of its 1990s-like
PDS.
We appreciated TeraSpeed's (Tom Dagostino and Dekker Graden) technical
insight and support in this investigation. And I should add that Tom Bingel
gets the credit, here at least in Honeywell, for first proposing this
explanation which initiated the measurements.
best regards,
Jim Peterson
Honeywell
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