[SI-LIST] IBIS about differential output

HI all
   I have a problem. When I generate an IBIS model for PCI-E driver. I
generate single output

IBIS model and use the model to do differential signal. 

I use [Diff Pin] keyword to do the differential output model.

When I simulation the IBIS file, I find that the common mode voltage
between positive node

and negative node is different that is the two output nodes have voltage
offset. How could I 

solve this problem? Thanks.

 

 


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List FAQ wiki page is located at:
                http://si-list.org/wiki/wiki.pl?Si-List_FAQ

List technical documents are available at:
                http://www.si-list.org

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

Other related posts: