[SI-LIST] : IBIS Vs SPICE matching issue

Hello All,

I sometimes observed that IBIS Vs SPICE matching issue.
IBIS data was  extracted from SPICE netlist simulation and printed in iBIS
format properly.
Stil there is some mismatch in SPICE netlist output and IBIS output.
Mismatch may be in form constant delay or in form of slower/faster response
as the output fall or rise.

- What are the reason for this and how it can be corrected?

- Also is there any documentation which tells how exactly all IBIS tables
(e.g. VI, rise VT, fall VT tables) are used in extracting output behaviour
of a circuit?

- how much accuracy is needed for IBIS usage point of view.

Thanks in advance.

Regards,
Sudhanshu



 

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