[SI-LIST] Re: IBIS Model for Multi-Chip Package


Hello Aaron:

  I believe what you want is an EBD (electrical board description) file as
described in the IBIS 3.2 specification.  Briefly, The EBD format allows you
to describe the die-die and die-pin interconnect using either lumped
elements or (perhaps more appropriately) transmission lines, and also ties
in with the .ibs files that describe the I/O buffers themselves.  For a copy
of the IBIS 3.2 spec visit

http://www.eigroup.org/ibis/specs.htm

 Hope this helps.

  Regards,
  Stephen Peters
  Intel Corp.


----Original Message-----
From: Aaron Frank [mailto:aaron@xxxxxxxxxxxxx]
Sent: Wednesday, July 25, 2001 7:25 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS Model for Multi-Chip Package



Hi All,

I am looking for feedback on how to accurately create an IBIS file for a
multi-chip package.
I have a device with several die on a single substrate, and my concern is
that simply lumping the package and driver parasitics will not represent the
substrate routing traces well enough.

For discussion purposes, assume the device package is a BGA containing two
die on a common substrate. Both die are connected in parallel, with most
signals going from the ball through a 1" trace to the die. Some signals are
star topology, some are daisychain.

For reference, the device is intended for clock speeds of 100-200MHz, with
very wide bus synchronous data transfers.

Options include:
  (a) Single IBIS file for complete package (preferred) with lumped
parasitics and ignoring substrate routing traces
  (b) IBIS of each die with recommendations on external transmission lines
(substrate) to connect them
  (c) Combination of IBIS of each die with Spice model of substrate
  (d) ?

Any opinions, tradeoffs, recommendations are appreciated.

Thanks,
AAron

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