[SI-LIST] Re: IBIS I/O model in HSPICE question

  • From: "Jon Powell" <jonpowell@xxxxxxxxxxxx>
  • To: <milabont@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 13 Feb 2003 08:45:05 -0800

Many IBIS simulators have no notion of "Control Input" for a buffer.
They generate their output based on user control but that control is usually
more like "go to high state" or "go to High-Z state" and not a voltage or
even
associated with what you would consider a voltage. They may perhaps take the
input
specification and use that to generate their controls but I do not think
that this
behavior is completely stated in the IBIS spec (I will take a look or let
someone else
yell at me).

Jon


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Mike LaBonte
Sent: Wednesday, February 12, 2003 10:36 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: IBIS I/O model in HSPICE question



Unlike the gate of a transistor, the control input of an IBIS 2.x buffer
is intended to be pure digital. I would be surprised if any simulator
has ordinary elements reading the control voltage, as opposed to a
software function checking the control voltage state to initiate IBIS
actions. In fact, the moment the control voltage is not zero an IBIS 2.x
buffer should initiate the rising waveform sequence and ignore the
control voltage value until the rising waveform completes or the control
voltage again reaches exactly 0V. The significance of 1V is to give a
corresponding voltage to test against for initiating the falling wave
sequence. I think simulators should sample the control voltage at the
end of the rise sequence and use that voltage as the reference for
detecting when to trigger a fall sequence, so that any voltage can be
used as the control input for the high state.

Now, if an IBIS 1.x model with no waveforms is used, it wouldn't surprise
me to find simulators using the control input in analog mode, proportionally
scaling the pullup and pulldown resistors. In this case the 1V level would
be a given, and higher control voltages might cause any kind of unexpected
math to work it's way through the model.

When I want to make an IBIS buffer behave more like a silicon transistor
model so that core level control voltages can be used, I wrap the IBIS
buffer
in a subckt that contains a voltage controlled voltage source to scale the
core level control signal down to 1V to make the IBIS buffer happy.

Mike

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ed Sayre III
Sent: Wednesday, February 12, 2003 6:16 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS I/O model in HSPICE question



Hi All,
    I am running an IBIS I/O model in HSPICE and have see some very strange
results dependant on the input voltage swing.  I am using the Ibis I/O in
the driver mode, driving a simple resistor load and another sim driving a
match terminated 25 Ohm tline and resistor load.  According to Page 18-43
of the 2000.2 manual either a 0-1V swing can be used for the input or a
typical 0-3.3V input swing can be used.  When I compare the outputs of the
I/O the two input level I find they are significantly different in wave
shape and peak overshoot. The 3.3V swing gives significant overshoot spikes
on the output node of the I/O model. When I look at the output current
(very clean and controlled, it would seem that ohms law is not observed,
this doesn't make sense.
     Does anyone have an idea of why this is occurring, and is it typical
of Ibis model outputs run in HSPICE  to behave differently dependant on
what voltage swing is applied to the input node of the driver??? BTW, I am
in direct contact with the vendor so I am interested in seeing if people
have seen this and if it is a model or an IBIS/HSPICE issue.

         Thanks in advance,
         -Ed


  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               NORTH EAST SYSTEMS ASSOCIATES, INC
                             -------------------------------------

                         "High Performance Engineering & Design"
  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  Dr. Edward Sayre 3rd            e-mail: esayre3@xxxxxxxx
  NESA, Inc.                              http://www.nesa.com/
  5 Lan Drive, Suite 200          Tel  +1.978.392-8787 x 218
  Westford, MA 01886 USA       Fax +1.978.392-8686
  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

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