[SI-LIST] Re: I need to compensate for component with too high an input capacitance.
- From: Yafei Bi <yafei_bi@xxxxxxxxx>
- To: Chris.Cheng@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Wed, 22 Mar 2006 16:15:07 -0800 (PST)
what is the definition of the input capacitance and
how it is measured? a LC meter or TDR? I believe they
are measuring different things.
most of the IC vendors list input/output capacitance
as a DC parameter. in that case, it is measured with a
LC meter and only counts the capacitance assoicated
with the pin.
is this correct?
Yafei Bi
--- Chris Cheng <Chris.Cheng@xxxxxxxxxxxx> wrote:
> This is an interesting problem. I have my share of
> excessive capacitance =
> from many vendors.
> My question is, why is it always excessive
> capacitance not under =
> capacitance. I've never seen one that have too high
> an impedance at the =
> pad. Or in another word, why does the I/O designer
> always under estimate =
> his/her pad capacitance ? Is it mostly due to under
> estimating the esd =
> structure ? Under estimate the bump capacitance ?=20
> And I am not talking about 50% off, I am talking
> about 2-3x off like the =
> problem listed below. Most vendor blames the package
> design but I found =
> it hard to believe.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of
> brimdavis@xxxxxxx
> Sent: Wednesday, March 22, 2006 7:45 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: I need to compensate for
> component with too high
> an input capacitance.
>
>
> ( re-posting, apologies if any duplicates show up )
> Tom wrote:
> >
> > They now claim that it is around 6 pF instead of 2
> pF. This, they
> > claim, is why driver with an 80 ps rising edge
> causes
> > such "excessive ringing" on the input.
> >
>
> If the problem is ISI from the {re}reflections off
> the big
> input C, one simple fix is to stick a differential
> pad in front
> of the reflective load - see further notes below.
>
> >
> > How best to do this? I have done some spice
> analysis on a circuit
> > that is known as the "constant resistance
> termination".
> >
> For another discrete-laden matching approach that
> can improve
> rise time for a big C, google "T-coil peaking".
>
> http://www.hagtech.com/pdf/tcoil.pdf
>
> Chapter 10, The Art and Science of Analog Circuit
> Design,
> Williams (ed.), 1995 ( chapter on T-coils )
>
> I've done simple inductive matching for narrrowband
> clock inputs,
> but have never been brave enough to try a fancier
> peaking scheme
> for, say, a 64 bit wide differential bus.
>
> >
> > 3) Is there an all together differenct aproach
> that I have not
> > thought of?
> >
>
> If you have net with plenty of signal margin,
> and/or a driver
> with adjustable output strength, a simple way to get
> rid of the
> ISI crud from the reflections is to put a
> differential attenuator
> ahead of the reflective input.
>
> As a differential attenuator preserves the line
> impedance,
> it doesn't further degrade the rise time, and it can
> be placed
> near, rather than exactly at, the end of the net.
>
> This approach also has the side effect of making
> the external
> signal probe-able by damping out the reflections if
> the probe point
> is upstream of the pad.
>
> You can get differential 100 ohm Zo attenuators in
> an 0404 size
> package, with values of 0,1,2,3,4,5,6, and 10 db,
> stocked at DigiKey.
>
> I recently posted some notes and simple simulations
> over on
> comp.arch.fpga, illustrating this same sort of
> problem for a
> fast non-back-terminated driver whacking an FPGA
> input with
> really big C; the posts below have further
> explanation and
> links to some pdf's and LTSpice files:
>
>
>
http://groups.google.com/group/comp.arch.fpga/msg/85db6dc0bca5c0da
>
>
http://groups.google.com/group/comp.arch.fpga/msg/ab999f47d42e50f8
>
>
http://groups.google.com/group/comp.arch.fpga/msg/95809af82ccbb550
>
> Note, the huge VCC clamp DC offset seen in the
> Xilinx V4 IBIS files
> from early March might have been fixed in their
> latest release.
>
> Brian
>
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