# [SI-LIST] Re: How to measure the On Die decupling capacitor value ?

• From: steve weir <weirsi@xxxxxxxxxx>
• To: Eddy <eddyvk@xxxxxxxxx>
• Date: Sun, 12 Sep 2010 14:27:18 -0700

```Measuring w/o bias is prone to a number of errors.  There are techniques
for measuring with bias applied, and those should be used.

In any event with deep submicron circuits I recommend you stay at or
below -20dB.  You should also make sure that you are using a DC block

Steve
Eddy wrote:
> A few notes:
> * When measuring the VDD to VSS capacitance without
> bias, be aware that all the on-chip circuitry connected to the power
> lines will also present a significant capacitance. Of course it depends
> upon the size of the circuit but there could be a few hundred pF from
> the circuit itself. However, you are most likely not interested in
> measuring the capacitance with 1% accuracy but rather want to know
> approximately how much is there (20~50% accuracy). For this purpose the
> measurement without bias is good. To be effective, the decoupling
> capacitance needs to be a lot bigger than the circuit capacitance
> anyway.
> * When measuring capacitance you are injecting a test signal.
>  Make sure this test signal does not affect the circuits other than the
> capacitance. When measuring without bias you want to stay below 0.4Vpp
> to not open any diodes in the circuit
>  that will affect the test result. This could for example be a reason
> for an unstable reading. Most network analyzers will default test with
> 0dBm signal level,
>  which would be too much. Lower the signal level to at least -10dBm.
> Theoretically the capacitance value should not be dependent upon signal
> level so you could try at different levels and determine for yourself
> how low your test signal level needs to be for a stable result.
> *
>  The fact that the chip needs on-chip power supply decoupling means that
>  there are signals inside the chip that might interfere with the power
> lines. When you apply bias the circuit becomes "alive" and signals from
> the chip might interfere with your capacitance test signals. This may be
>  another reason for an unstable test result. If possible put the chip in
>  a sleep mode or
> powered down mode so there can be no other signals than your test signal
>  on the power lines. When powering up only an I/O power pin it might be
> OK but
>  there can still be diodes between the I/O power line and other power
> lines so you could still be partly powering other circuits.
> * Capacitance meters
>  can have a bias setting but usually this is not strong enough to power a
>  chip. Make sure that when you set for example Bias=1.8V that the DC
> voltage on your chip is actually going up to 1.8V.
> * To minimize the
> influence from bond wires and other leadframe parasitic inductance you
> can use a low test frequency like 10MHz or perhaps as low as 1MHz. The
> lower the test frequency, the smaller the error in your capacitance test
>  from parasitic inductance.
> * When one node for your test probe or test signal is the ground plane
>  then you can use S11. The VSS of your chip is most likely connected to
> the ground plane. When you need to do a differential test between two
> nodes then I would recommend S12 (or S21). Most network analyzers have
> built in functionality to convert S parameters to impedance.
> * Before
>  hooking up your test system and test methods
>  to the chip, first verify with a known capacitor that your method is
> working OK. Take for example a 1000pF (1nF) capacitor and verify that
> your equipment is indeed measuring something close to 1000pF. It can
> save you a lot of trouble and a lot of time to first make sure that your
>  test method is OK.
> I hope these notes will help you getting good test results for the on-chip
> decoupling capacitance. ;-)
>
> Eddy van Keulen
> Sr Applications Eng. Mgr.
> San Jose, CA - USA
>
>
> --- On Fri, 9/10/10, yardala <yardala@xxxxxxxxx> wrote:
>
> From: yardala <yardala@xxxxxxxxx>
> Subject: [SI-LIST] How to measure the On Die decupling capacitor value ?
> To: si-list@xxxxxxxxxxxxx
> Date: Friday, September 10, 2010, 7:15 PM
>
> Hi, All
> Can I measure the value of On Die Decoupling capacitor use only capacitor
> meter
> probing at  pin Vdd and Vss ?
>
> When I use meter to measure the value of core logic are few nH and unstable,
> the value of I/O power are several hundred pF.
>
> Does these value make sense ? does it good enough , or any other methods are
> suggest ?
>
> Does the bonding wire effect the capacitor value ?
>
> Thanks!
>
> Yardala
>
>
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Steve Weir
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