[SI-LIST] Re: How to get I/V curves in IBIS by simulation?(not using s2ibis)
- From: "Tom Dagostino" <tom@xxxxxxxxxxxxx>
- To: <cat_carl@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sun, 30 May 2004 20:20:36 -0700
Cat
If the large currents occur between ground and Vcc then I would be
concerned. If the large currents are in the clamp areas (below ground or
above Vcc) then it is likely that the clamp diodes are not modeled correctly
in SPICE. In many cases the clamp device model does not include the
intrinsic resistance of silicon or has some other issue.
The VT curves should only be simulated into a purely resistive load when
making the model. In the real application on a circuit board it is the
simulator's job to apply the reactive load to the model. That simulation
should show the response of the buffer to the reactive load.
When the buffer is in a tristate model none of the output devices should be
on. You will see only the effects of any clamp devices that may be present.
There should be about zero current between ground and Vcc. Below ground and
above Vcc (if a power clamp is present) you should see a classic diode
characteristic.
Tom Dagostino
Teraspeed Consulting Group LLC
503-430-1065
tom@xxxxxxxxxxxxx
www.teraspeed.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of maoxin yin
Sent: Monday, May 31, 2004 10:29 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] How to get I/V curves in IBIS by simulation?(not
using s2ibis)
Hello everyone,
Maybe the mail subject is not exact. There is a question about the V/T
curve.And the problems are about output pads and tri-states.
I am trying to make IBIS model for our chip. I have tried S2ibis and in some
sense it works. But I got real problems when I made I/V curves or, say, the
I/V curves seemed odd. There are very large currents, about 8A or larger.
I did the simulation following IBIS cookbook'guide. I think the simulation
setup enviroment of IBIS cookbook is the reason for these large currents. As
it mentions, an output buffer is mainly consisted of a PMOS and a NMOS(for
sketch). Then its setup is to connect a controlled voltage source at the
output pad and make the votage source to swing between -Vcc and 2*Vcc.
As I know, whatever the output state is(low/high/tri), one of the MOS will
be turned on. And I found in our pads that to enlarge the driving capacity,
there are in fact several such Mos pairs in parallel. This caused the large
currents.
Well, is this setup really valid? and if it is, what does these large
currents mean? I originally think this means when there are reflections big
enough, the large currents will occur. But this disaster never happened
though in some cases the reflection was there.
Then a question about the V/T curve. The cookbook advises to use a series
resistor as load. But there will be a big difference between a capacitive
load and a resistive load, isnt it? And on PCB, the buffer will connect to
transmission lines which, as I think, is at least capacitive in part.
OK, these questions may seem naive. But can anyone be so kind to help me
out?
Thanks.
Regards.
cat
May 31,2004
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