[SI-LIST] How to get I/V curves in IBIS by simulation?(not using s2ibis)

  • From: "maoxin yin" <cat_carl@xxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 31 May 2004 10:28:38 -0700

Hello everyone,
Maybe the mail subject is not exact. There is a question about the V/T 
curve.And the problems are about output pads and tri-states.
I am trying to make IBIS model for our chip. I have tried S2ibis and in some 
sense it works. But I got real problems when I made I/V curves or, say, the I/V 
curves seemed odd. There are very large currents, about 8A or larger.

I did the simulation following IBIS cookbook'guide. I think the simulation 
setup enviroment of IBIS cookbook is the reason for these large currents. As it 
mentions, an output buffer is mainly consisted of a PMOS and a NMOS(for 
sketch). Then its setup is to connect a controlled voltage source at the output 
pad and make the votage source to swing between -Vcc and 2*Vcc.

As I know, whatever the output state is(low/high/tri), one of the MOS will be 
turned on. And I found in our pads that to enlarge the driving capacity, there 
are in fact several such Mos pairs in parallel. This caused the large currents.

Well, is this setup really valid? and if it is, what does these large currents 
mean? I originally think this means when there are reflections big enough, the 
large currents will occur. But this disaster never happened though in some 
cases the reflection was there.

Then a question about the V/T curve. The cookbook advises to use a series 
resistor as load. But there will be a big difference between a capacitive load 
and a resistive load, isnt it? And on PCB, the buffer will connect to 
transmission lines which, as I think, is at least capacitive in part.

OK, these questions may seem naive. But can anyone be so kind to help me out?
Thanks.

Regards.
cat
May 31,2004
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