[SI-LIST] Re: How many bond-wires to make a good PDS?

Graham,
Steve is right on the money with the bond wire question. Unless your die is
core limited with respect to the IO, it is always difficult to get enough
wirebonds in. This is why you really need to look at what the on-die
decoupling will be. You need to supply enough decoupling to provide for
stable power over multiple cycles to allow the wire-bond inductance effects
to be minimized. For an interface running at high rates (667MHz or faster),
I found that an average of 50pf/IO (minimum) was required even with the high
s/r ratio.
You also need to keep track of what is coupling within the bond-wire region.
In most designs, the VDD bonds are longer than the VSS bonds and the signal
bonds are the longest of all. Maintaining good signal isolation and return
propeties takes careful consideration

 Doug

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of steve weir
Sent: Monday, December 03, 2007 3:28 PM
To: nemisonic@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: How many bond-wires to make a good PDS?

Graham, the answer is probably a lot more than you would like.  The bond 
wire portion of the inductance loop will depend on factors such as: 
proximity to other power bond wires of each polarity, bond wire length 
and the shape of the arc.  A starting number would be around 10nH for 
one pair by the time you get to the PCB.   If you are pumping out 
100-150ps edges, and have good hf bypass on die, then one power / gnd 
wire pair for every four signals should get you in the ballpark. 

I caution you to make sure that you make it feasible for your end 
customer to package a realizable PDN on their PCB.  The cheap package 
that you are going into pretty much precludes on-substrate caps, so you 
are forcing the bypass problem down to your customer where it is even 
harder to solve.  If you put too much inductance between your customer's 
plane attachment and your die the game is over.

Good luck.


Steve.

Graham Kus wrote:
> Hi everyone,
> So I have a question. When designing a power supply distribution system
> (PDS) for an FBGA bond-wire ASIC package, how many bond-wires are
"enough?"
> I understand that 25um(1 mil) diameter bond-wires can accommodate almost 1
> Amp at DC, but I suspect this is completely off base when driving a bus
with
> one of these.
>
> The background on my situation involves DDR-2 drivers, and having enough
> bond-wires to prevent SSO. This IC package is an FBGA, 4 layer substrate
> board. The IP vendor supplied pin-based RLC charts for a lead-frame type
> package (although I have yet to see DDR-2 in a TSSOP). These translate
well
> to signal routes, but the physics the PDS are different than lead-frame
pin
> structures.  Also this vendor's numbers for power are based literally on a
> "rule of thumb chart," which to me is code for "open your SI tool and
double
> check." We wrestled them into giving us Spice versions of the buffer under
> NDA, so presumably we can simulate this ourselves. Anyhow if you guys have
> advice, I could use it.
>
> Thanks in advance,
>
> -Graham
>
>
> [gmail search terms: bondwire bond-wire wirebond wire-bond]
>
>
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