[SI-LIST] Re: How Do Others Do Timing Analysis Without Tool Like BLAST

Harold,

What a great question!

The methods and complexity of system level timing analysis depend on a
variety of factors, including:

* % mix of standard components vs. ASIC/FPGA devices
* Whether device timing is specified at die pad, device pin, or elsewhere
* Conditions under which timing is specified
* Clocking schemes: common clock, clock forwarded, or hybrid schemes

Timing analysis provides a model of an interface into which flight time data
from SI analysis can be integrated, to determine if the interface will
operate at a particular speed.  Understanding the details of how timing
models and flight time measurements fit together is critical, and becomes
more involved as transfer rates go up.

I can think of three approximate categories of complexity, each of which
tend to have the same sorts of approaches to timing/SI analysis:

1. Low Speed (Few ASIC/FPGAs, timing to pin, common clock 75 MHz or less)

Paper and pencil works just fine for the timing model, and SI analysis is
used to ensure flight times stay below some target.

2. Moderate Speed (Some ASICs/FPGAs, timing to pin, common clock, 75-150
MHz)

Smaller margins mean the timing model needs to be more precise.  Many people
build timing models for specific interfaces in Excel and use that to
determine timing budgets for common clock designs operating in the 100 MHz
range.  There's an old joke about Excel being the world's most widely used
CAE/CAD tool, which just happens to be true.  Flight times from SI analyses
are put back into the spreadsheet to determine if the interface meets
timing.

3. High Speed (Lots of ASICs/FPGAs, timing to die pad, clock forwarded,
150MHz +)

As the margins get smaller, the need to model the "tracking" behavior of
different parts of the interface becomes greater.  For example, in a clock
forwarded interface, when the data driver is slow, the clock driver will be
be slow as well, minimizing the skew between the two signals (as opposed to,
say, a common-clock interface).  Of course, clock-forwarded interfaces tend
to operate a high transfer rates, so the reduction in skew is essential for
the interface to operate at all.

In these interfaces, the details will make or break you:  where and how
timing is measured, how the package is modeled for SI analysis,
characterization of SSO effects, etc.  You can still try and take all the
different timing relationships and model them in an Excel spreadsheet, but
the process becomes quite complex.

We routinely analyze clock-forwarded designs operating at 100's of MHz, and
have found that there just don't seem to be any good, commercially available
tools/processes for combining ASIC and system, SI and timing data.  There
are lots of products that analyze different pieces of the puzzle, but
putting the pieces together in a design flow is ultimately the
responsibility of the user.  We use tools that let us interactively build
detailed timing models of an interface, and then ensure that the different
pieces of the puzzle (ASIC path delays, PCB flight times, etc.) are
calculated in such a way that all the pieces of the puzzle fit together
properly.

I don't have personal experience with either BLAST or Tau, and can't comment
on how well they would perform on the problems and frequencies we work with.
I have no doubt that these tools would work just fine for 100 MHz,
common-clock designs.  We've asked for examples of people using these tools
for high speed, clock forwarded interfaces, but simply haven't heard that
much feedback.

Hope that helps,

Todd.

Todd Westerhoff
SI Engineer - Hammerhead Networks
5 Federal Street - Billerica, MA - 01821
email:twester@xxxxxxxxxxx - ph: 978-671-5084
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