[SI-LIST] Re: How Do Others Do Timing Analysis Without Tool Like BLAST

 Hi Adrian,

How does it matter to have a complicated topology
as long as the Address/Data take the same time 
(within calculated tolerances) to reach a receiver as the clock (out of the 
clk_out pin)does?

Please explain.

I do agree on tools for prelayout SI analysis.

Thanks,
- Raja

--

On Fri, 21 Sep 2001 10:03:53  
 Grigoras, Adrian C wrote:
>
>Lucky dude !
>What if you had a complicated topology ? That is why you need to run *some*
>simulation tool just to make sure your timings are met ( using the various
>methodology existents ) and there are no signal integrity problems.
>My  2 cents .. literally these days :-)
>Adrian 
>
>
>-----Original Message-----
>From: Raja Patil [mailto:raja.patil@xxxxxxxxx]
>Sent: Friday, September 21, 2001 9:51 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: How Do Others Do Timing Analysis Without Tool
>Like BLAST
>
>
>
>Hi Michael,
>
>I don't understand what you mean by generating routing guidelines by doing
>pre-layout timing analysis.
>
>Consider a memory interface with Clk,Adr, and data lines. What I do is to do
>a static timing analysis-mainly hand calculation. This gives me whether
>there is any set-up/hold time violation or the margins I have. Then What I
>do is to route these signals of *almost* equal length or maintain the diff
>within the length given by margin(ns)*6in/ns(speed on the trace). I don't do
>anything else.
>
>Have I been damn lucky with my work or 
>this is exactly what the tools(BLAST etc.) do?
>
>regards,
>- Raja
>--
>
>On Fri, 21 Sep 2001 10:03:41  
> Greim, Michael wrote:
>>
>>Hi Harold,
>>
>>There are any number of ways that one can do static timing
>>analysis and there are a number of tools that one can perform
>>this analysis with.  I think that the biggest barrier to 
>>entry with most of these tools is cost.  Going to a show 
>>like designcon will expose you to the number of vendors that 
>>produce these tools and what the price spectrum may be.  The
>>second element to this is what your tool flow is and how 
>>information can be passed forward and backward.  By performing
>>pre-layout timing analysis you can create a set of constraints 
>>that can be used to drive your router.  This prelayout analysis
>>can also set up your timing budget which can also help drive 
>>your placement and find errors early in the design process.
>>Errors found after routing are costly from both a dollar cost 
>>and schedule perspective.  These constraints 
>>can also be used to generate drcs so your timing errors can
>>be easily found at the physical implementation.   Often times 
>>timing analysis will be performed prior to placement to see 
>>if the flight times have a reasonable budget.  The timing can
>>then be performed after placement using the manhatten lengths
>>of the routes to perform timing and finally after routing.  
>>When done properly the post route sim should be quick and relatively
>>uneventful.  
>>
>>I hope that this helps.
>>
>>Just my 0.02
>>
>>best regards,
>>
>>Michael Greim
>>
>>-----Original Message-----
>>From: polus@xxxxxxxxxxx [mailto:polus@xxxxxxxxxxx]
>>Sent: Friday, September 21, 2001 9:39 AM
>>To: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] How Do Others Do Timing Analysis Without Tool Like
>>BLAST
>>
>>
>>
>>
>>
>>Greetings Everyone!
>>
>>How do the rest of you perform timing analysis. WE have XFX but not BLAST.
>>Currently I do it in EXCELL with a home grown internal tool. This is
>>cumbersome
>>and time consuming.
>>
>>There has to be a better way, particularily for pre-layout design rather
>>than
>>having to wait for post layout data and using something like BLAST.
>>
>>Any suggestions?
>>
>>Harold Polus
>>Lexmark Laser Printer Controller Development
>>SI & EMC
>>
>>
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