[SI-LIST] Hidden noise margin problems

SI Community,
Is it common for the Vih and Vil on a datasheet to be specified under
worst-case conditions (70/30% VDD w/ VDD @ min/max conditions), while the
IBIS model for the part only specifies Vih and Vil at VDD @ nominal (even
thought the model may have min and max VI and VT corners)?

I've now found this to be the case on two completely different parts from
completely different manufacturers.  What it seems to create is a worst-case
simulation that appears to behave fine, but a worst-case noise margin
calculation (based on the datasheet) that has little to even negative noise
margin.

Case in point:

Driver has spec'd Voh = 2.4V and the receiver has a Vih = 0.7 * VDD = 0.7 *
3.465V = 2.4255V 

-25.5 mV of noise margin

However, the net simulates just fine across all corners (model Vih = 2.31)


Is this a common problem?  I would think that Vih and Vil in the model
should match that in the datasheet, especially if is dependant on the rail
voltage of the part.

Comments?


Regards,

Tim Nash

__________________________________
Timothy J. Nash, P.E.
Honeywell, Inc.
Defense & Space Electronic Systems
13350 U.S. Hwy 19 N
M/S 105-4
Clearwater, FL  33764-7290
Office : 727-539-2437
Fax     : 727-539-2183
Email  :  tim.j.nash@xxxxxxxxxxxxx


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