[SI-LIST] Re: HSTL Buffer


Ron,

So your all set to go. Just drive the twisted pair and terminate at the far
end with a differential terminator (dependent on your T-line impedance).
Since your driving from one board to the next you might have to watch out
for common mode differences between driver and receiver. The HSTL
specification is 0.68V-0.9V input common mode range for the receiver. This
is narrow. Due to ground mismatch on the separate boards you may drift
outside of this narrow specification. On the other hand if the HSTL
designer has designed a much wider tolerance to common mode variation (due
to architecture choice) you may not have to worry about common mode range.
The LVDS spec is a lot better on the common mode range. It is from 0-2.4V.
Effectively the power supply range.

--------------------------------------------------------------
| Bill Cohen
| Toshiba America Electronic Components, Circuit Design Group
| email: wcohen@xxxxxxxx
| office: (508) 486-1031               fax: (508) 481-8828
--------------------------------------------------------------


                                                                                
                                    
                    "Ron Mancuso"                                               
                                    
                    <ron.mancuso@co       To:     <Bill.Cohen@xxxxxxxxxxxxxxxx> 
                                    
                    rrent.com>            cc:                                   
                                    
                                          Subject:     RE: [SI-LIST] HSTL 
Buffer                                    
                    02/20/02 07:39                                              
                                    
                    PM                                                          
                                    
                                                                                
                                    
                                                                                
                                    




Can't choose.  The other board is designed by another company - I have to
interface to it.  The ASIC I have to use, also uses HSTL - can't change
that either.


Also, by the way, these are neither Class I or II, but differential HSTL
which eliminates the need for a reference voltage.


Thanks,
Ron


-----Original Message-----
From: Bill.Cohen@xxxxxxxxxxxxxxxx [mailto:Bill.Cohen@xxxxxxxxxxxxxxxx]
Sent: Wednesday, February 20, 2002 4:18 PM
To: Ron Mancuso
Cc: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] HSTL Buffer






Ron,


I have designed HSTL class I & II HSTL buffers. While the receiver is
technically differential the signalling is really single ended with a
reference signal. The termination is designed for either far end or near
and far end (Class I/II differences). I would think LVDS would be a much
better choice. I have seen several ads in tech journals for standard LVDS
driver and receivers. LVDS can be terminated on the far end using
differential termination (not tied to a reference).


--------------------------------------------------------------
| Bill Cohen
| Toshiba America Electronic Components, Circuit Design Group
| email: wcohen@xxxxxxxx
| office: (508) 486-1031               fax: (508) 481-8828
--------------------------------------------------------------





I'm looking at an application where differential HSTL is run from board
to board via twisted shielded pair.  I'm investigating the option of
possibly adding buffers to strengthen the signals both as they leave and
enter the board I'm designing.  Any tips on how to do this or parts that
can do this?  Also, I'm assuming that since this is differential
signaling, I wouldn't need the VTT terminator - but I would rather be
wrong now than later.  :)


Any input would be appreciated.


Thank you,
Ron Mancuso
Corrent Corporation


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