[SI-LIST] Re: HSPICE - Deciding Max. route length

  • From: Bi Han <mike_bihan@xxxxxxxxxxxx>
  • To: siva@xxxxxxxxxxxxxxxxx, List` Si <si-list@xxxxxxxxxxxxx>
  • Date: Sun, 5 Oct 2003 16:01:47 +0800 (CST)

The first question on Nand power related much to difinition, what need 
attention was the input power consumption to drive the gate caps of NAND.
The second quesion on max route length was pretty confusing. Is the major 
concern of length related to "the delay" of the lines, which will translate to 
clock skew issue or setup/hold time issue?
 
Wish real experts can help answer.
 
Han

Siva Krishna <siva@xxxxxxxxxxxxxxxxx> wrote:
Hi All,
Presently I am learning HSPICE.
From the tool point of view I have found so many documents.
But from the concepts point of view I did not find any documents.
Can anybody suggest good documents, books or sites etc.

Concepts means, for example, if I want to calculate the power 
consumption of a NAND cell,
then what are the various types of vectors/inputs I need to 
apply and where the power has to be measured etc.

Similarly, can anybody suggest how to decide max. route length 
in a design.
I heard that for each design, by doing some spice simulations 
the max. route length will be decided
and in the P&R of that design they will take care such that the 
net length will not exceed that limit.

Thanks in advance for your help.

Thanks & Regards,
Siva Krishna.


-- 
"To vanquish without danger
is to triumph without glory "

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