[SI-LIST] Re: Guidlines required for high speed PCB design

Rajeev,
what you have mentioned is a widely adapted practice. Yet how many vias
should be drilled on blank signal areas is a question. I feel too many of
them will actually reduce the real-estate of the ground plane and contribute
a little bit towards looping of return current through ground plane path.
So, another practice could be adapted here. Have a Chassis grounding running
across the boundary of the board and stitch it strongly with the ground
plane. And tentatively select the number of signal-plane stitching drills.

Regards,
Subramanya

----- Original Message -----
From: "Rajiv Kumar Gupta" <rajiv_gupta@xxxxxxxxxxxx>
To: <iain.lochhead@xxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
Sent: Wednesday, February 26, 2003 5:26 PM
Subject: [SI-LIST] Re: Guidlines required for high speed PCB design


>
> Hello,
>
> can we add to it:"Guidlines required for high speed PCB design stack up"
> Ground plane power plane & signal layers respective position in PCB =
> stack up,
> stitching vias to GND, GND spread over vacant space on signal layer,
> SMD,crystal placement and layoutetc to reduce the noise
> especially when one deals with High freq signal ,audio signal,HF digital
> signal& power.
> I feel this will be quite helpful to all the designer especially the
> beginners
>
>
> Regards
> Rajiv
>
>
> -----Original Message-----
> From: Iain Lochhead [mailto:iain.lochhead@xxxxxxxxxxxxxxx]
> Sent: Wednesday, February 26, 2003 5:01 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Guidlines required for high speed PCB design
>
>
> Dear all,
> =20
> I have been tasked with providing some guidance with regard to routing
> high speed differential signals to/from our SerDes device. The device is
> packaged in 81 ball BGA package.=20
> The device can be used in 300pin 10Gbps Optical Transponder module
> applications and also for use on line cards. I have designed high speed
> boards for SerDes parts and also designed
> boards for high speed 10Gbps serial parts, so I do have some
> understanding of the signal integrity issues that should be considered.
> However, I have not used BGA packaged parts and had to consider escape
> routing of signals from inner rows of such packages. The parallel data
> to/from the SerDes part are differential LVDS running at rates up-to
> 1.25Gbps. I need to obtain a better understanding of the following
> issues to understand whether the ball assignments will create Signal
> Integrity issues relating to routing of the differential bus. Can anyone
> provide feedback or sources of reference for investigation into the
> following:-
> =20
> *         Common layer stack/material selection used for Transponder
> module board / Line card designs.
> *         Common strategies for escape routing of differential signals
> from BGA packages.
> *         Feedback on types of impedance controlled structures commonly
> used to reduce layer count and increase density
> *         Routing schemes for minimizing crosstalk between pairs=20
> *         Guidelines for BGA ball-out assignments to support ease of
> routing and to maintain signal integrity
> =20
> At this stage in the design process, I am able to provide feedback to
> the design team to enable optimized ball out for both signal integrity
> and for routing. I have read some interesting application notes from a
> number of sources, incl Altera & Zilinx relating to high speed board
> layout using BGA packages - these provided useful information. I would
> like to pursue these subject area's further and would really appreciate
> some feedback.
> =20
> Best Regards
> =20
> =20
> Iain Lochhead
> Design Validation & Test Engineering Manager
> Phyworks Ltd
> =20
>
>
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