[SI-LIST] Re: Ground plane voids under Tip/Ring
- From: pwelling@xxxxxxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 10 Jan 2002 09:14:46 -0700
Bob,
A couple of things that I forgot to mention.
It is assumed that the traces from the magnetics to the connector are short.
Longer traces may create other problems specifically based on operating
frequency (loos - usually not with E1, T1, 10-Base-T, maybe 100-Base-T in
low crosstalk environments), and GOOD Signal Integrity design of the rest of
the board.
We usually route the traces as side-by-side (edge coupled)differential
matched pairs unless there is a connector problem. This helps to prevent PWB
Prepreg mis-registration problems that can happen. It also prevents
differential noise in higher crosstalk environments (a trace coupling noise
to one differential pair element and not the other).
There should be good spacing from the trace pair to any other traces - even
in adjacent layers.
We typically cover the trace/voided area with Chassis Ground Planes on the
top and bottom layers of the PWB. This is tied to Chassis Ground as locally
as possible. This usually still meets the regulatory concerns and provides
local containment inside the cabinet for self compatibility.
In this configuration, you will have to calculate the impedance differently.
Depending on where you place the traces, you may have a symmetrical
Stripline Differential pair or Asymmetrical Stripline Differential Pair.
Philip Ross Wellington
Mgr. Signal Integrity & EMI
L-3 Communications CSW
-----Original Message-----
From: pwelling@xxxxxxxxxxxxxxxxxxx [mailto:pwelling@xxxxxxxxxxxxxxxxxxx]
Sent: Thursday, January 10, 2002 8:12 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Ground plane voids under Tip/Ring
Bob,
There are a few reasons for voiding the planes (signal reference planes)
around E1, T1, 10-Base-T, 100 Base-T, etc.
The first one is for EMI. These traces are generally high impedance 75, 100,
122, 150 Ohms, and it is easy for digital planes noise to couple to the
traces (after all, the reference plane is part of the impedance of the
trace). This digital noise is coupled via the plane to the traces and exits
your cabinet as common mode noise (not differential which could be cancelled
out by the receiver). Most, but not all, of these interfaces are unshielded
twisted pair cables. The common mode noise present on the cable pair becomes
radiated emissions which may cause you to fail EMI/EMC compliance testing.
If the planes are voided then there is much less likelihood of the common
mode noise coupling to the traces and causing the raditated emissions.
The second problem is that you may induce an EMI/EMC susceptibility problem.
During immunity testing, the product is subjected to intentional radiation
(in Volts/Meter) to induce failures. The severity of the immunity testing
may range from 3 Volts/Meter to 1000's of Volts/Meter depending on what
standard you must meet. The frequency sweep range and dwell time is also a
function of the test standard (may be from 10 KHz to 40 GHz).
Your cable connected to the E1, T1, etc, port will see this as common mode
noise again. If the common mode noise is referenced to a digital (or
sensitive analog reference plane), that common mode noise will be impressed
on that plane(s). The noise is always trying to return to the source (it
tries to get there from ground), and will distribute over your PWB planes
until it finds it through the path of least inductance. It may (and very
likely will), pass along several sensitive digital chips with PLLs, clocks,
analog mixers, modulators, demodulators, etc, and cause problems. If the
planes are voided then there is much less likelihood of the common mode
noise coupling to the planes and causing the susceptibility problems.
Using Shielded cabling helps with both of these problems because you contain
the radiated emissions from the board and provide a local preferred return
path (the short shield connection to chassis ground) to minimize the loop
inductance.
A third reason is that some regulator agencies (FCC, PTT, etc) require them
to be voided and for all exposed copper to be voided by a certain distance
away from the traces. This is to prevent noise coupling to the PBX and phone
network and improve immunity. There was an application note from Dallas
Semiconductor a few years ago the gave that distance.
It is always better to prevent problems than fix them later. At 3:00 A.M.,
the lab creates a humble engineer, submissive to a great teacher -
experience.
There probably other reasons for voiding the planes, if there are, I would
be interested in your comments.
I hope this helps.
Philip Ross Wellington
Mgr. Signal Integrity & EMI
L-3 Communications CSW
-----Original Message-----
From: Bob Patel [mailto:whizplayer@xxxxxxxxx]
Sent: Wednesday, January 09, 2002 5:55 PM
To: si_list
Subject: [SI-LIST] Ground plane voids under Tip/Ring
Hi! I had a question regarding the design of T1, T3
interfaces i.e. in all the designs the portion from
the TIP & Ring(outside world interface) upto the
primary side of transformer is void of any ground
planes.
Is this to meet any immunity, safety, EMC requirement?
Thanks in advance
Bob
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