[SI-LIST] Re: Ground clearance at connector vias

Hi Fabrizio,

One thing to definitely do is TDR the path through the
connectors and backplane. You will find it pretty illuminating.
The thing that will amaze you is the big speed bump (or speed "valley"
actually) that you will see for the big plated-through hole associated
with the connector pins, through a .250 thick backplane. It tends to
look capacitive, so there is a big dip in the TDR plot. This is where
most of your discontinuity will come from, at least in the cases I
have looked at. You will have to play games with the anti-pad and pad =
diameters of the PTH to try and minimize the discontinuity. Generally
you end up increasing the anti-pad a bit (yet still maintain some
ground web on the plane layers between pins). It is also a big deal as
to which layers you route on in the backplane and what the via stubbing =
looks like. You want to give preference to your GHz signals to have a
minimum via stub.

Ken



-----Original Message-----
From: Fabrizio Zanella [mailto:fzanella@xxxxxxxxxxxx]=20
Sent: Thursday, March 27, 2003 7:50 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Ground clearance at connector vias


I have a question regarding ground clearances for signal vias in a
backplane connector, like the Molex/Teradyne HSD.  Connector and
semiconductor manufacturers recommend using an oval ground clearance
around the differential pairs, to minimize reflections.
Do you agree with this recommendation, especially at signal speeds of
2.5Gbs and above?  Can anyone share their experiences?  How large should
the clearance be on the backplane?

Thanks and regards,

Fabrizio Zanella
Principal Hardware Design Engineer
Broadbus Technologies
fzanella@xxxxxxxxxxxx
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