[SI-LIST] Re: Ground Pours

  • From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
  • To: "Gary Schneider" <gschneider@xxxxxxxxx>
  • Date: Wed, 1 Mar 2006 09:55:38 -0800

Gary,

I see a warapage waiver box, but it is not checked.  I'll forward this to
John Stephens as he is the author of the last set of comments and see what
he has to say.

Sure are some determined people out there who need to jsutify inner layer
signal fills!


> [Original Message]
> From: Gary Schneider <gschneider@xxxxxxxxx>
> To: <leeritchey@xxxxxxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Date: 3/1/2006 9:12:28 AM
> Subject: RE: [SI-LIST] Ground Pours
>
> Lee,
>
>  There is a warpage waiver on the Merix stack up supplied by Merix.
> We don't have a problem because we flood fill. On some of our 14 and 16
> layers it was recommended by Merix to flood fill or allow thieving on
> inner layers that did not contain dense routing. The stack up had the
> warpage waiver check with the explanation in the comments line.
>
> Gary
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Lee Ritchey
> Sent: Wednesday, March 01, 2006 10:16 AM
> To: si-list
> Cc: John Stephens
> Subject: [SI-LIST] Ground Pours
>
> Here is a response from John Stevens of Merix to the discussion about
> ground pours in signal layers.  John has been at this for many years and
> engineers some of the most complex multilayer PCBs in the world.  His
> company is a leader in this field.   I hope this cuts through some of
> the confusion on this topic.  He also supplied a recent stackup from
> Merix and it does not contain any disclaimer about adding thieving on
> inner layers.
> I included all of the string leading up to this for those who want the
> history.
>
> Lee,
>
> Wow what a string!
>
>  Since I have been building board since 1974 guess I am qualified to
> retort.
>
> So let's try to set the record straight on this.
>
> Thieving or adding copper pours to internal signal or plane layers does
> not help etching in any way as you indicated. The biggest problem
> etching is dense circuitry patterns with tight spacing and isolated
> traces. The isolated traces can get over etched as it is harder to
> clear the tight spacing (.004 or less) on long parallel runs. Thieving
> cannot be placed close enough to a trace for electrical reasons to
> improve this condition. So we learn to etch better. Or even
> selectively compensate isolated traces.
>
> They started to get closer to the issue when discussing lamination.
> Adding thieving or copper pours to signal layers may improve dielectric
> control (prepreg thickness) but it is minimal at best, especially if we
> are talking about 1/2 oz copper. 
>
> Thieving signal layers can improve registration control if you have very
> sparse circuitry as it will improve the dimensional stability of the
> layers.
>
> The part about split planes is accurate. Don't use 2 mil or less ZBC
> type plane pairs with big open areas in the same place on both layers.
> The problem is in handling you can crack them where they want to fold
> since there is no copper. Use a solid ground plane on one side, problem
> solved.
>
> The 2 big reasons for internal thieving is for flatness control or low
> pressure areas on high layer count boards. If the design had all of the
> copper cleared out of the planes layers along one edge for high voltage
> or other reason (could care less about signal layers) there will be the
> risk of getting air entrapment, due to the low pressure area created.
> The thicker the copper the greater the risk. One way of minimizing this
> risk without thieving is by using separator plates between boards in a
> lamination book. With the advent of CAC (copper aluminum copper) to
> replace foil lam and plates, many folks have a bigger issue with getting
> uniform pressure in a big stack of boards with only the thin aluminum
> between each board. So they are compensating for their process.
> Thieving those areas make sense and we typically ask customers to do so
> and tie them to ground if they like. All of this can be avoided if you
> use a little bit higher resin content and slightly thicker dielectrics
> and you know how to laminate. (how old fashioned are we?)
>
> If the board stack up is unsymmetrical to the extent that it will warp,
> using solid copper pours to create a pseudo balance stack up will help
> improve the flatness. If the stack up is balanced from a signal/plane
> configuration I don't care how much copper is missing from the signal
> layers the board is still going to be flat. Even a high layer count
> board that is slightly unbalanced will be flat given all the solid plane
> layers.
>
> Lastly,
> I attached a recent Merix stack up we did for John Z at Caspian, don't
> see any generic disclaimer on thieving. We do ask to thieve outer
> layers for plating density to control copper in the holes and on the
> surface so we plate and etch the outer layers better. The thieving
> helps etch by making the plating thickness more uniform, but you already
> knew that.
>
> I think that covers it. You are so right when you mention how much myth
> and misuse of information there is out there.
>
> I need a glass of wine now.
> John
>
>
> -----Original Message-----
> From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx] 
> Sent: Tuesday, February 28, 2006 2:00 PM
> To: Stephens, John
> Subject: FW: RE: [SI-LIST] Re: Ground Pour in Signal Layers
>
> Is this true?
>
> Lee Ritchey
> Speeding Edge
> P.O. Box 2195
> Glen Ellen, CA
> 95442
>
> Phone- 707-568-3983
> FAX- 707-568-3504
>
> I just used the energy it took to be angry and wrote some blues.
> Count Basie
>
>
> > [Original Message]
> > From: Gary Schneider <gschneider@xxxxxxxxx>
> > To: <leeritchey@xxxxxxxxxxxxx>; Charles Grasso
> <Charles.Grasso@xxxxxxxxxxxx>; Gerry Gagnon <mrgagman@xxxxxxxxxxx>;
> <rhaller@xxxxxxxxxxxxx>
> > Cc: <si-list@xxxxxxxxxxxxx>
> > Date: 2/28/2006 12:09:38 PM
> > Subject: RE: [SI-LIST] Re: Ground Pour in Signal Layers
> >
> > All,
> >
> > We have worked with Merix for quite sometime and they have a waiver
> on
> > their stack up sheet. It is a warpage waiver if you do not flood fill
> or
> > thieve. Granted it depends on layer count, thickness, and complexity
> of
> > board.
> >
> > Gary Schneider
> > Design Services Manager
> > X-EMI
> > 12708 Riata Vista Circle
> > Austin, Tx 78727
> > Main 512.493.9660
> > Fax 512.493.9661
> > Direct 512.493.9672
> > Cell 512.773.7174
> > Email gschneider@xxxxxxxx
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of Lee Ritchey
> > Sent: Tuesday, February 28, 2006 12:08 PM
> > To: Charles Grasso; Gerry Gagnon; rhaller@xxxxxxxxxxxxx
> > Cc: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> >
> > Might want to check with the process engineers at Merix or TTM on this
> > one.
> >
> >
> > > [Original Message]
> > > From: Grasso, Charles <Charles.Grasso@xxxxxxxxxxxx>
> > > To: <leeritchey@xxxxxxxxxxxxx>; Gerry Gagnon <mrgagman@xxxxxxxxxxx>;
> > <rhaller@xxxxxxxxxxxxx>
> > > Cc: <si-list@xxxxxxxxxxxxx>
> > > Date: 2/28/2006 9:34:58 AM
> > > Subject: RE: [SI-LIST] Re: Ground Pour in Signal Layers
> > >
> > > How interesting! I have not had to deal with thieving on inner
> layers
> > > so I popped down to our layout group and asked our folks there. The
> > > consensus was - YES - Thieving on inner layers can be necessary and
> > > should be used for unbalanced layouts. Indeed one former employee of
> > DDI
> > > indicated that DDI had a program that automatically added thieving
> > > based
> > > on the design. The reason for adding the thieving is to avoid
> warpage.
> > >
> > >
> > > Best Regards
> > > Charles Grasso
> > > Senior Compliance Engineer
> > > Echostar Communications Corp.
> > > Tel: 303-706-5467
> > > Fax: 303-799-6222
> > > Cell: 303-204-2974
> > > Pager/Short Message: 3032042974@xxxxxxxx
> > > Email: charles.grasso@xxxxxxxxxxxx;
> > > Email Alternate: chasgrasso@xxxxxxxx
> > >
> > >
> > > -----Original Message-----
> > > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > > On Behalf Of Lee Ritchey
> > > Sent: Tuesday, February 28, 2006 9:44 AM
> > > To: Gerry Gagnon; rhaller@xxxxxxxxxxxxx
> > > Cc: si-list@xxxxxxxxxxxxx
> > > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> > >
> > > Gerry,
> > >
> > > I'm not sure what length of involvement has to do with this, but if
> it
> > > is
> > > important, I've been at it PCB fab since 1969 and have crawled
> through
> > > perhaps 250 PCB shops all over the world, most recently in November
> of
> > > 2005.
> > >
> > > Virtually all of what I have designed and had fabricated are high
> > speed
> > > PCBs and adding thieving to the inner layers has never been
> necessary
> > > and
> > > is not now.
> > >
> > > As to who I consider the best shops in the world, that's a subject
> for
> > > off
> > > line discussion as adivising clients on this matter is part of my
> > > specialty.
> > >
> > >
> > > > [Original Message]
> > > > From: Gerry Gagnon <mrgagman@xxxxxxxxxxx>
> > > > To: <leeritchey@xxxxxxxxxxxxx>; <rhaller@xxxxxxxxxxxxx>
> > > > Cc: <si-list@xxxxxxxxxxxxx>
> > > > Date: 2/27/2006 5:36:57 PM
> > > > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> > > >
> > > > Lee,
> > > >
> > > > Sorry but I gotta defend my old pal Rob.
> > > >
> > > > I started in PWBs back in 1978 and have been there ever since. By
> my
> > > count 
> > > > that's 28 years with the last 8 or so exclusively in design &
> supply
> > > chain 
> > > > support.
> > > >
> > > > I know of NO creditable lamination engineer tasked with gluing
> many
> > > cores 
> > > > together who would ever complain about getting properly theived
> > inner
> > > signal 
> > > > layers. Theiving innerlayers provides a similar benefit to resin
> > flow 
> > > > characteristices that external theiving provides to pattern
> plating.
> >
> > > > Especially with tight dielectric thickness tolerances, resin
> content
> >
> > > > tolerances, thick or different copper weights, and tight warpage
> > > specs. I 
> > > > have built many hi layer count, high speed boards using
> autotheiving
> > > on 
> > > > inner and outerlayers. Most could not have been done without it.
> > > >
> > > > I will say that there is minimal benefit for the lower PWB
> > > technologies,
> > > so 
> > > > if you design these types of products, you are getting the right
> > > advice.
> > > >
> > > > BTW - Having crawled through a few shops in my day (now focussed
> > more
> > > on
> > > the 
> > > > Far East, India, and Eastern Europe), I'm curious as to who you
> > > consider
> > > the 
> > > > best fabricators in the world to be today?
> > > >
> > > > Regards,
> > > >
> > > > Gerry Gagnon
> > > >
> > > >
> > > >
> > > > ----Original Message Follows----
> > > > From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
> > > > Reply-To: leeritchey@xxxxxxxxxxxxx
> > > > To: "Robert Haller" <rhaller@xxxxxxxxxxxxx>
> > > > CC: si-list@xxxxxxxxxxxxx
> > > > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> > > > Date: Mon, 27 Feb 2006 12:13:56 -0800
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> > > >
> > > > Bob,
> > > >
> > > > If you don't mind sharing the names of those process engineers
> with
> > > us,
> > > I'd
> > > > appreciate it. I'd like ot speak with them myself as that data
> > flies
> > > > directly in the face of the advice from the best fabricators in
> the
> > > > industry.
> > > >
> > > >
> > > > > [Original Message]
> > > > > From: Haller, Robert <rhaller@xxxxxxxxxxxxx>
> > > > > To: <leeritchey@xxxxxxxxxxxxx>
> > > > > Cc: <si-list@xxxxxxxxxxxxx>
> > > > > Date: 2/27/2006 11:14:07 AM
> > > > > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> > > > >
> > > > > Lee,
> > > > > I spoke with a few process engineers and have learned
> something,
> > > > > and felt compelled to respond to inform (I do not intent to
> > > offend).
> > > > >
> > > > > Copper pour or thieving on inner layers, I have been told by
> two
> > > > > separate processing engineers can lead to "better lamination",
> > and
> > > as
> > > > > always it depends on the circuit.
> > > > >
> > > > > One example is if you are using very thin cores (i.e. BC) and
> the
> > > > > circuit has large areas void of copper you may get curling. The
> > > final
> > > > > layer stack may yield poor lamination (delamination), have
> > > increased
> > > > > stresses and possible registration issues. =20
> > > > >
> > > > > PCB processes today have not changed that much (in fact they
> have
> > > > > changed too little IMHO when compared to semiconductor
> advances),
> > > so I
> > > > > would respectively disagree that the past is in fact
> relevant.=20
> > > > >
> > > > > Regards,
> > > > > Bob=20
> > > > >
> > > > > -----Original Message-----
> > > > > From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx]=20
> > > > > Sent: Thursday, February 23, 2006 5:41 PM
> > > > > To: Haller, Robert; Chris Padilla (cpad); ivorlist@xxxxxxxxxxx;
> > > > > Pradeep.RSA@xxxxxxxxxxxx
> > > > > Cc: si-list@xxxxxxxxxxxxx
> > > > > Subject: RE: [SI-LIST] Re: Ground Pour in Signal Layers
> > > > >
> > > > > Etching and plating are two very different operations. Plating
> > > depends
> > > > > on
> > > > > uniform current distribution. Etching is done by spraying
> > etchant
> > > onto
> > > > > the
> > > > > surface and proceeds at the same rate over the entire surface.
> > All
> > > you
> > > > > gotta do is ask a process engineer at a currently operating fab
> > > shop to
> > > > > see
> > > > > if thieving is needed on inner layers. every time I ask, the
> > > answer is
> > > > > no.
> > > > >
> > > > > What may have been at some point in the past is not relevant.
> > What
> > > is,
> > > > > is
> > > > > what todays' fabricators need and theiving on inner layers is
> not
> > > one
> > > of
> > > > > them..
> > > > >
> > > > >
> > > > > > [Original Message]
> > > > > > From: Haller, Robert <rhaller@xxxxxxxxxxxxx>
> > > > > > To: <leeritchey@xxxxxxxxxxxxx>; Chris Padilla (cpad)
> > > <cpad@xxxxxxxxx>;
> > > > > <ivorlist@xxxxxxxxxxx>; <Pradeep.RSA@xxxxxxxxxxxx>
> > > > > > Cc: <si-list@xxxxxxxxxxxxx>
> > > > > > Date: 2/23/2006 11:54:20 AM
> > > > > > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> > > > > >
> > > > > > Lee, Chris
> > > > > > I worked in a board shop many years ago. My understanding
> of
> > > the
> > > > > > original intention of adding thieving to signal layers was to
> > > promote
> > > > > > consistent etching (or plating) and as a result even
> > distribution
> > > of
> > > > > > etch widths. The chemical process of etching inner layers is
> in
> > > > > general
> > > > > > more consistent if there is an even distribution of copper
> > across
> > > the
> > > > > > panel (subtractive or additive processes - etching or plating
> > > both
> > > > > > benefits).=3D20
> > > > > >
> > > > > > There are numerous subtleties like etching/plating varies
> from
> > > center
> > > > > to
> > > > > > edge of the panel and what specific type of additive or
> > > subtractive
> > > > > > processes, chemicals, electro plating, ... you are using.
> > > > > > =3D20
> > > > > > As folks have pointed out you must be very careful with
> spacing
> > > to
> > > > > > critical signals and adjacent layer stripline pairs.=3D20
> > > > > >
> > > > > > We had some interesting arguments at the dinner table when
> > > > > > "Auto-thieving" was first introduces at Digital - my brother
> is
> > a
> > > > > > Chemical Engineer, my mom is a Produce-ability
> (Manufacturing)
> > > > > Engineer
> > > > > > and I am an EE .....
> > > > > >
> > > > > > Regards,
> > > > > > Bob Haller
> > > > > > Enterasys Networks=3D20
> > > > > >
> > > > > >
> > > > > >
> > > > > > -----Original Message-----
> > > > > > From: si-list-bounce@xxxxxxxxxxxxx
> > > > > [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > > > > > On Behalf of Lee Ritchey
> > > > > > Sent: Thursday, February 23, 2006 12:31 PM
> > > > > > To: Chris Padilla (cpad); ivorlist@xxxxxxxxxxx;
> > > > > Pradeep.RSA@xxxxxxxxxxxx
> > > > > > Cc: si-list@xxxxxxxxxxxxx
> > > > > > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> > > > > >
> > > > > > Chris,
> > > > > >
> > > > > > Of the three reasons listed below, only number 2 is of value.
> > > Shield
> > > > > > islands don't really do that. They may induce cross talk.
> > > > > Fabricators
> > > > > > don't need fill in signal layers to prevent warpage. I'm not
> > > sure
> > > > > where
> > > > > > that one got started. Also, doesn't help control impedance,
> > but
> > > > > rather,
> > > > > > can make it drop if the fill is too close.
> > > > > >
> > > > > > Don't mean to offend anyone with these answers, but the
> record
> > > needs
> > > > > to
> > > > > > be
> > > > > > set straight.
> > > > > >
> > > > > >
> > > > > > > [Original Message]
> > > > > > > From: Chris Padilla (cpad) <cpad@xxxxxxxxx>
> > > > > > > To: <ivorlist@xxxxxxxxxxx>; <Pradeep.RSA@xxxxxxxxxxxx>
> > > > > > > Cc: <si-list@xxxxxxxxxxxxx>
> > > > > > > Date: 2/23/2006 8:53:40 AM
> > > > > > > Subject: [SI-LIST] Re: Ground Pour in Signal Layers
> > > > > > >
> > > > > > > "Ground" pour can serve several purposes:
> > > > > > >
> > > > > > > (1) Create shielded islands
> > > > > > > (2) Create some extra interplane capacitance (not sure how
> > > useful
> > > it
> > > > > > is
> > > > > > > for charge storage as it is most likely located
> electrically
> > > far
> > > > > from
> > > > > > > the chip needing the current)
> > > > > > > (3) Balance out a layer to avoid warpage issues and to
> ensure
> > > better
> > > > > > > trace dimension (impedance) control
> > > > > > >
> > > > > > > I think (3) is the big one: Fab shops often request the
> > > ability to
> > > > > > add
> > > > > > > "thieving" in areas of sparse metal. Some folks just go
> > ahead
> > > and
> > > > > add
> > > > > > > the metal pour and often sink several "ground" vias through
> > it
> > > to
> > > > > > > connect it up to something. I forget the details why, but
> > the
> > > fab
> > > > > > shops
> > > > > > > have better control of trace width if they don't have to
> etch
> > > away
> > > a
> > > > > > lot
> > > > > > > of metal.
> > > > > > >
> > > > > > > As in all cases, such items can cause problems if not
> > carefully
> > > > > > handled
> > > > > > > and thought through.
> > > > > > >
> > > > > > > Chris Padilla
> > > > > > > Cisco Systems
> > > > > > > San Jose, CA
> > > > > >
> > > ------------------------------------------------------------------
> > > > > > To unsubscribe from si-list:
> > > > > > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the
> Subject
> > > field
> > > > > >
> > > > > > or to administer your membership from a web page, go to:
> > > > > > //www.freelists.org/webpage/si-list
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> > > > > > For help:
> > > > > > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject
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> > > > > >
> > > > > > List FAQ wiki page is located at:
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> > > > > > List technical documents are available at:
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> > > > > >
> > > > > > List archives are viewable at: =20
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> > > > > > or at our remote archives:
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> > > > > > Old (prior to June 6, 2001) list archives are viewable at:
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> > > > > > =20
> > > > >
> > > > >
> > > > >
> > ------------------------------------------------------------------
> > > > > To unsubscribe from si-list:
> > > > > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject
> > > field
> > > > >
> > > > > or to administer your membership from a web page, go to:
> > > > > //www.freelists.org/webpage/si-list
> > > > >
> > > > > For help:
> > > > > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> > > > >
> > > > > List FAQ wiki page is located at:
> > > > > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
> > > > >
> > > > > List technical documents are available at:
> > > > > http://www.si-list.org
> > > > >
> > > > > List archives are viewable at:
> > > > > //www.freelists.org/archives/si-list
> > > > > or at our remote archives:
> > > > > http://groups.yahoo.com/group/si-list/messages
> > > > > Old (prior to June 6, 2001) list archives are viewable at:
> > > > > http://www.qsl.net/wb6tpu
> > > > >
> > > >
> > > >
> > > > ------------------------------------------------------------------
> > > > To unsubscribe from si-list:
> > > > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject
> > field
> > > >
> > > > or to administer your membership from a web page, go to:
> > > > //www.freelists.org/webpage/si-list
> > > >
> > > > For help:
> > > > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> > > >
> > > > List FAQ wiki page is located at:
> > > > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
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> > > > List technical documents are available at:
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> > > >
> > > > List archives are viewable at:
> > > > //www.freelists.org/archives/si-list
> > > > or at our remote archives:
> > > > http://groups.yahoo.com/group/si-list/messages
> > > > Old (prior to June 6, 2001) list archives are viewable at:
> > > > http://www.qsl.net/wb6tpu
> > > >
> > > >
> > > > ------------------------------------------------------------------
> > > > To unsubscribe from si-list:
> > > > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject
> > field
> > > >
> > > > or to administer your membership from a web page, go to:
> > > > //www.freelists.org/webpage/si-list
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> > > > For help:
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> > > >
> > > > List FAQ wiki page is located at:
> > > > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
> > > >
> > > > List technical documents are available at:
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> > > >
> > > > List archives are viewable at: 
> > > > //www.freelists.org/archives/si-list
> > > > or at our remote archives:
> > > > http://groups.yahoo.com/group/si-list/messages
> > > > Old (prior to June 6, 2001) list archives are viewable at:
> > > > http://www.qsl.net/wb6tpu
> > > > 
> > >
> > >
> > > ------------------------------------------------------------------
> > > To unsubscribe from si-list:
> > > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject
> field
> > >
> > > or to administer your membership from a web page, go to:
> > > //www.freelists.org/webpage/si-list
> > >
> > > For help:
> > > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> > >
> > > List FAQ wiki page is located at:
> > > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
> > >
> > > List technical documents are available at:
> > > http://www.si-list.org
> > >
> > > List archives are viewable at: 
> > > //www.freelists.org/archives/si-list
> > > or at our remote archives:
> > > http://groups.yahoo.com/group/si-list/messages
> > > Old (prior to June 6, 2001) list archives are viewable at:
> > > http://www.qsl.net/wb6tpu
> > > 
> >
> >
> > ------------------------------------------------------------------
> > To unsubscribe from si-list:
> > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >
> > or to administer your membership from a web page, go to:
> > //www.freelists.org/webpage/si-list
> >
> > For help:
> > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> > List FAQ wiki page is located at:
> > http://si-list.org/wiki/wiki.pl?Si-List_FAQ
> >
> > List technical documents are available at:
> > http://www.si-list.org
> >
> > List archives are viewable at: 
> > //www.freelists.org/archives/si-list
> > or at our remote archives:
> > http://groups.yahoo.com/group/si-list/messages
> > Old (prior to June 6, 2001) list archives are viewable at:
> > http://www.qsl.net/wb6tpu
> > 
> >
> >
>
>
>
>
>
>
>
> Lee Ritchey
> Speeding Edge
> P.O. Box 2195
> Glen Ellen, CA
> 95442
>
> Phone- 707-568-3983
> FAX- 707-568-3504
>
> I just used the energy it took to be angry and wrote some blues.
> Count Basie
>
>
> -- Binary/unsupported file stripped by Ecartis --
> -- Type: application/pdf
> -- File: 28L_100919-05FD_12-12-05.pdf
> -- Desc: 28L_100919-05FD_12-12-05.pdf
>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> //www.freelists.org/webpage/si-list
>
> For help:
> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
> List FAQ wiki page is located at:
>                 http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>
> List technical documents are available at:
>                 http://www.si-list.org
>
> List archives are viewable at:     
>               //www.freelists.org/archives/si-list
> or at our remote archives:
>               http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
>               http://www.qsl.net/wb6tpu
>   
>


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List FAQ wiki page is located at:
                http://si-list.org/wiki/wiki.pl?Si-List_FAQ

List technical documents are available at:
                http://www.si-list.org

List archives are viewable at:     
                //www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

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