[SI-LIST] Re: Fwd: Re: About the chassis gnd and logic gnd

Steve,
For digital electronics we almost always get the lowest radiated and
conducted emissions, and the highest electromagnetic/electrostatic
discharge (ESD) immunity, by using multipoint grounding between chassis
ground and logic ground.  But this is an area where I like to provide
"wiggle room", because sometimes we get nasty surprises when we actually
test our prototype hardware.  For example, I had a card that I designed
about 1995, where I spent two solid weeks cycling between radiated
emissions tests, ESD immunity tests, and lightning surge susceptibility
tests, trying to come up with *a* solution that would pass all three
tests.  I finally succeeded, but it was a very aggravating experience.  

So what I usually do (this is covered in chapter 27, and on pages 31-79
to 31-82 of Robust Electronic Design Reference Book (REDRB)) is:
*  Run an input-output ground in all layers, along the edge of a board
   that has connectors going to the "outside world".
*  Connect the input-output ground to logic ground with "ground ties", 
   nominally 0.050" wide traces, on the top and bottom of the board at
   the ends of the input-output ground and about every 2 to 3" along
   the moat between the two grounds.  We can easily cut these ground 
   ties with an X-acto knife if we want to isolate the two grounds
   partially or completely.
*  Parallel the ground ties with pads or plated-through holes, letting
   us replace each ground tie with a capacitor, ferrite bead, inductor,
   or resistor if we want to change to a hybrid-ground system.
*  Connect the input-output ground to the chassis, mounting plate,
   shield, etc., with a reliable bond (see pages 31-79 to 31-81, chapter
   33, and appendix E of REDRB Volumes 1 and 2).
*  If the board is large enough that we will need additional support 
   points, put a logic ground ring about each mounting hole on the 
   bottomside of the board.  Design the housing so that we can use 
   either metal stand-offs to provide additional chassis ground-to-
   logic ground connections, or plastic standoffs to isolate them.

In many cases we're not smart enough to know which grounding/return
technique will work best, especially when doing a completely new
design.  So consider all the grounding/return schemes that we might want
to use, and figure out ways to implement any of them just by
adding/removing/ changing components, and maybe doing some judicious
carving on prototype boards.  Even when we are confident about the best
way to go (and I can be pretty darned cocky in this area), design in
flexibility and then let the EMC/EMI/EMI tests be our guide.  Having to
respin a board to change the grounding/return scheme, when we could have
allowed for it up front in a design, can be a mighty-expensive mistake
both in time and money.

                John Barnes KS4GL, PE, NCE, ESDC Eng, SM IEEE
                dBi Corporation
                http://www.dbicorporation.com/
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List FAQ wiki page is located at:
                http://si-list.org/wiki/wiki.pl

List technical documents are available at:
                http://www.si-list.org

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: