[SI-LIST] Faraday Cage for Hi Speed ADC
- From: "RakeshBit" <rakesh@xxxxxxxxxxxxx>
- To: "SI LIST" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 8 Sep 2008 17:21:08 +0530
Hi All,
We are doing a Hi speed (1Gsps) ADC design. I find most of the off the shelf
boards available with similar specifications have a Faradays Cage around the
ADC portion of the Board.
1. Could any one throw some light on the design issues involved in designing
Faradays Cage fro this application.
2. Point to literature / application notes ...etc. to enable us to take this
design forward.
Regards
Rakesh Mehta
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
- » [SI-LIST] Faraday Cage for Hi Speed ADC
