[SI-LIST] FW: eye diagram

Karan:

Eye diagrams as specifications are normally found on optical transmitters, 
where the optical output needs to meet a normalized mask, built into test 
equipment like Agilent DCA's.   The most common eye diagrams are for binary (1 
or 0)signaling.  Test method is very important and the test points, load 
impedances, single-ended vs differential must be specified in order to make 
accurate comparisons.  Also for some devices, errors are pattern dependent so 
data pattern as well as data rate needs to be specified.  System bandwidth is 
very important as a lot can be missed (apparently cleaned up) by using a 
filter, although many standards like SONET, will specify eye mask using filters 
with their order, type and cutoff frequency specified.

Eye patterns quantify the amount of amplitude noise and time variation (or 
jitter) which will "close" the eye diagram vertically and horizontally.  An eye 
pattern is an overlaying of the transition (1-0 & 0-1) shapes of all the 
different possible combinations of bit patterns.  Depending on standard or 
datasheet, typically a PRBS pattern will be used, although eye diagrams of 
other non-random data patterns can also be examined.

Eye pattern masks also put limits on the amount of overshoot and undershoot.  
Many SONET documents (like GR-253) call out transmitter eye pattern masks for 
OC-3, OC-12, OC-48 data rates.  

Similar masks are also developed for Copper.  They may specify minimum eye 
heights, or a mask.  Some circuits like SerDes chips are able to retime 
incoming data and recover data even if the eye is completely closed and 
undiscernable on the scope.  Many times, eye pattern responses are used to 
qualitatively compare performance of digital signaling devices.  There is also 
the concept of mask margin (in %), which is basically a more stringent mask 
beyond the standard specification.  Most high-speed scopes will allow you to 
dial this in until you start to see mask hits.  We talk about mask "hits" or 
errors that occur and we can qualitatively look to see if we are close to 
operating error free and whether the eye is open or clean.  To get BER, 
however, it is best to use BERT.

To relate it to SI, excessive losses of cables and PCB's will close your eye 
vertically, mismatched impedances will add ripple which will increase overshoot 
and close the eye, while run length differences can help close the eye 
vertically.  Of course there are a lot of effects from the IC's themselves 
(clock jitter, amplitude balance, skew) which impact the eye and may be 
impossible to change once signals are in your PCB.

For more, I would check for App. Notes on the Agilent 86100 DCA products.  And 
I see now Art Porter from Agilent has just recommended a netseminar, even 
better.

Good Luck !!

Jeff LaT.

-----Original Message-----
From: karan bagga [mailto:kbagga31@xxxxxxxxx]
Sent: Monday, September 29, 2003 1:37 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] eye diagram


Hi,
 
Want to know about eye diagram.
How does eye diagram plays a role in desiging Multi Gigaherts PCBs ?
What is the methodology i.e do eye diagrams come in datasheets.
Need some basic understanding on relation with eye diagram and SI.
 
Regards
Karan

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