[SI-LIST] Re: FW: Re: Microstrip/Stripline

Bob - I like the summary, and have added my own comments.  In general, I
think Eric said it well about there not being a single solution - it all
depends!

Microstrip usually has
        Higher crosstalk.  >>> Agreed - for given trace spacings which,
in most real designs, you want to keep to a minimum.
        More difficult to control Z0.  >>> Absolutely agreed.  I haven't
seen any TDR measurements otherwise, and I've seen tons agreeing
(including lots of my own).
        Lower dielectric losses (not including Solder mask). >>> I
question this (please see below)
        Can avoid via stubs.  >>> Sometimes. In real designs, I often
end up with via stubs because I can't route everything on microstrip, or
I'm forced to have test points.

>>> About the loss question...
Eric's comments got me looking at my data again (that lead me to believe
the losses of microstrip and stripline are equivalent).  That data was
based on simulations (XFX -> Hspice), which my past experience has shown
to correlate well to measurements.  Assuming the trace width and
thickness is kept constant (adjusting the dielectric thickness to
achieve the proper impedanct), it showed little difference between
microstrip and stripline for our current frequencies of interest (say,
up to ~5GHz).  I also validated this using ADS, but would love to see
anyone's conflicting data.  I should point out that this is with
soldermask, which I'm assuming most designs will be forced to use.
Similar experiments with pure microstrip (no soldermask) showed
microstrip to be slightly less lossy than stripline.

I also went searching for empirical data comparing microstrip vs.
stripline (with trace width/thickness kept constant), and could only
come up with differential insertion loss data (which my experience shows
to be about the same as single-ended) from some previous test boards.
Again, this data suggests there isn't a significant difference in
insertion loss between microstrip (ms) and stripline (sl).

designator      ms/sl   length  SDD21 (dB/inch) SDD21 (dB/inch) SDD21
(dB/inch)       SDD21 (dB/inch) SDD21 (dB/inch)
                        (inches)        @ 2GHz          @ 5GHz
@ 10GHz         @ 15GHz         @ 20GHz
tx              ms      3.70            -0.31322                -0.63756
-1.09496        =09
ty              ms      6.72            -0.32799                -0.68239
-0.93585                -1.41054                -1.94654
tz              ms      14.73           -0.29535                -0.65554
-1.24440                -1.77721                -1.94088
sx              sl      4.70            -0.32201                -0.84455
-1.39444                -2.82177                -2.89115
sy              sl      10.70           -0.30822                -0.70208
-1.39162                -2.40874                -2.47964
sz              sl      20.00           -0.31697                -0.68828
-1.10133                -1.72593                -2.18520

Hopefully, this table will make it through somewhat recognizable.

When I look at this data, here's what I see:
(1) at 2GHz, there's no difference (as expected - conductor loss
dominates)
(2) at 5GHz, "sx" has significantly more loss than the rest - but hard
to believe it's solely because it's stripline.
(3) at 10GHz, 2 of the striplines exhibit more loss, but the longest
stripline ("sz", which is probably the most reliable, due to its long
length), shows the same as the microstrips (actually less than the
longest microstrip, "tz").
(4) roughly the same trend as (3) continues up to 20GHz (the data from
the shortest microstrip, "tx", was too noisy to make sense of).

The dimensions were:
ms: h=3D3.5, w=3D5, s=3D5, t=3D1.4; microstrip had soldermask on it.
sl: h1=3Dh2=3D6, w=3D5, s=3D5, t=3D1.4
Standard FR4 was used.

From this data, I would hesitate to make any conclusions regarding the
relative losses of microstrip vs. stripline.  Do others have data?

Disclaimer:
The content of this message is my personal opinion only and although I
am an employee of Intel, the statements I make here in no way represent
Intel's position on the issue, nor am I authorized to speak on behalf of
Intel on this matter.=20

Jeff Loyer

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Ray Anderson
Sent: Monday, December 19, 2005 8:36 AM
To: si-list@xxxxxxxxxxxxx
Cc: Ray Anderson
Subject: [SI-LIST] FW: Re: Microstrip/Stripline

Forwarded to the list for Bob (rhaller@xxxxxxxxxxxxx)

-----Original Message-----
From: Haller, Robert [mailto:rhaller@xxxxxxxxxxxxx]=3D20
Sent: Monday, December 19, 2005 6:31 AM
To: ray.anderson
Subject: [SI-LIST] Re: Microstrip/Stripline

Ray Can you please post this to Si-list (until such time as we resolve
my posting issues)
----------------------------------------

This Micro-strip Strip-line thread is an interesting discussion that I
have previously pursued off-line with a few colleagues/list members. I
would love to see hard bench data that is a true apple to apples
comparison in time and frequency domains. =3D20

I have past experience in board shops and typical Micro-strip processes
do exhibit higher variations and until recently always preferred
stripline environments. But recent 2D/3D simulations have led me to
believe that Micro-strip can be designed to produce 'longer' working
links. =3D20

A number of folks I have discussed this issue with agree that=3D20
        Microstrip usually has
                Higher crosstalk=3D20
                More difficult to control Z0=3D20
                Lower dielectric losses (not including Solder mask)
                Can avoid via stubs =3D20
        Stripline usually has
                Lower crosstalk
                Homogenous environment (except for glass weave)
                Higher dielectric losses
                Via stubs

But what happens when you are routing high-speed differential networks
(Module and/or Backplanes) and you want to accurately compare theses 2
unique environments with similar routing densities.

Equivalent line widths/lengths between stripline and microstrip,
Microstrip with LPISM (Solder mask) and no via stubs, Microstrip
conductor shape not as well controlled.

Dual stripling - Single reference plane (second plane far away),
Stripline with Via stubs.

Regards, Bob

Robert Haller
Enterasys Networks
Core Routing - Hardware
Phone: 978-684-1340=3D20
FAX:     978-684-1499


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