[SI-LIST] FW: Ground clearance at connector vias

Greetings Fabrizio:

Ansoft is a contributor to the XFP MSA (www.xfpmsa.org).  We contributed
differential via analysis and optimization for 62mil and 100mil PCBs.  Our
results indicate that for 10Gb/s transmission, differential vias with a
0.8mm via pitch, 0.3mm drill size, and 0.56mm pads, had best performance
(lowest return loss) using a gap of 0.52mm.  The "gap" is the distance from
the pad to the oval-shaped ground (or power) clearance keepout.
Interestingly, the optimized dimensions for both 62mil and 100mil board
thicknesses are identical.  This can be explained by considering the via
structure as a transmission line with propagation along the dimension
perpendicular to the PCB plane.  It is intuitive that this transmission line
should have a uniform cross-section that is independent of the length of the
line (board thickness).

We also performed analyses of ground-signal-signal-ground (GSSG)
differential via structures.

You can examine all of the results in Appendix D of the XFP specification
available at

http://www.xfpmsa.org/XFP_Rev_2.pdf

Hope this helps.

Best regards,

Larry

___________________________________
Lawrence I. Williams, Ph.D.
Director of Business Development
Ansoft Corporation

1-714-528-9358
1-714-747-5894 cell
___________________________________
williams@xxxxxxxxxx
www.ansoft.com

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Fabrizio Zanella
Sent: Thursday, March 27, 2003 4:50 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Ground clearance at connector vias



I have a question regarding ground clearances for signal vias in a
backplane connector, like the Molex/Teradyne HSD.  Connector and
semiconductor manufacturers recommend using an oval ground clearance
around the differential pairs, to minimize reflections.
Do you agree with this recommendation, especially at signal speeds of
2.5Gbs and above?  Can anyone share their experiences?  How large should
the clearance be on the backplane?

Thanks and regards,

Fabrizio Zanella
Principal Hardware Design Engineer
Broadbus Technologies
fzanella@xxxxxxxxxxxx
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