[SI-LIST] Re: FPGA package jitter - Troubleshooting idea

Tom,
You may be able to get some insight in what generates the jitter if you compute 
the FFT of your measured signals and try to correlate it with specific 
activities in the FPGA Core.  I've done a similar analysis in my entry paper to 
the "Discover Your True EyeQ Contest" early this year.  If you are interested 
you can download a free copy of that paper from the contest hosting website if 
you search the Internet for it, or you can get there following one of the links 
in the "News and Events" section of NoiseCoupling.com website 
http://www.noisecoupling.com . 
Cosmin Iorga
NoiseCoupling.com
http://www.noisecoupling.com
   




________________________________
From: Tom Sylla <tsylla@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Friday, September 18, 2009 8:26:53 AM
Subject: [SI-LIST] FPGA package jitter

We are running an 8-bit LVDS interface between an Altera Stratix II
(EP2SGX60EF1152C3N) and a Xilinx Virtex-5 SXT50 (XC5VSX50T-3FFG1136C).
The protocol is a stripped-down version of HyperTransport, running at
800MT/s. The channel is all on PCBs, no cables, between a
daughterboard and baseboard connected over a diff-pair style
connector.

Most of the logic in the Xilinx part is dedicated to running a core
created by Xilinx System Generator running at 50MHz. We first noticed
CRC errors detected by the receiving Altera FPGA, depending on the
load put on the Xilinx core. After some narrowing of the problem, it
was clear that there was a great deal of jitter on the LVDS clock and
data coming out of the SXT50. The jitter is present whenever the 50MHz
core domain is "busy". With that domain in reset, there is little
jitter and we can pump data through the LVDS with no problem.

We verified that the jitter does not depend on the data pattern coming
out of the LVDS. We also checked that it was not being introduced by
clock spin-up inside the FPGA. We tried PLLs, DCMs, combinations of
the two, and also no spin-up. The jitter was always there.

Of course, our first suspicions were everything under our own control
(our own board design). We verified that the jitter is not being
introduced by our crystals or other clock sources. We reviewed and
compared our PDN design to the Xilinx recommendations and Xilinx
reference designs, and our design seems better in all regards. We
reviewed the layout, and compared it closely to the Xilinx PCB
Designer's Guide for the SXT. The most interesting thing to note from
the Guide is that *no* small caps are supposed to be required on any
of the rails for the Virtex-5. Even with that recommendation, we had
12 0402 .1uF capacitors present on the 1.0V core voltage (in addition
to an array of larger values). We have 1 plane layer and 3
polygon-on-signal layers connecting the regulator output and the
center of the BGA. The 3 signal layer shapes are all coupled to solid
ground planes, so we should have very good inter-plane capacitance. We
did try quite a few different capacitor value changes, up, down,
mixed, none, etc, but there was little effect.

To explore the power supply quality, we did a common ripple
measurement setup: remove one of the small caps from under the BGA,
and probe the voltage there. The 1.0V core voltage cannot be driven
out on I/O pins, so we could not do "spyhole" measurements. Our ripple
was well within the Virtex's spec of ±5% (we measured ~50mV out of the
100mV spec). The ripple magnitude did not change a great deal
depending on the load applied, only the frequency components in the
ripple changed. This was further verified by use of an external quiet
bench supply providing the 1.0V core voltage; the jitter was just as
bad with this.

Xilinx would not try our setup on one of their internal boards, so we
bought the ML506 reference board (with the same SXT50 part and
package), and it failed the same way. The jitter has the same
characteristics as it does on our board. I added some links to some
scope shots of the jitter on the reference designs at the end of this
mail. We also purchased a Virtex-4 board (ML402) and also saw the core
frequency getting on to the LVDS outputs. Basically, completely
different PCB designs show the same jitter problems.

We did get some guidance from Xilinx to try and move our core to a
higher frequency to move away from potential resonance problems. When
we moved to 100MHz, things did get better, but we still see jitter
added onto the LVDS. What is most unique about our setup is that we
are using the DSP48E blocks inside the Xilinx part very heavily, and
they seem to have huge power requirements.

For the SI-Listers, we are sort of wondering if anyone else has seen
this issue in the virtex series and what sort of solutions might be
possible. It *seems* like our PDN is working ok at the board level,
since the ripple measurements look ok.

Thanks for any thoughts,
Tom Sylla



ML506 (Virtex-5) quiet core domain:
http://picasaweb.google.com/pastepic/XilinxJitter#5382819303667903346
ML506 (Virtex-5) busy core domain:
http://picasaweb.google.com/pastepic/XilinxJitter#5382819308850505698

ML402 (Virtex-4) quiet core domain:
http://picasaweb.google.com/pastepic/XilinxJitter#5382819323724657490
ML402 (Virtex-4) busy core domain:
http://picasaweb.google.com/pastepic/XilinxJitter#5382819311825794226
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