[SI-LIST] Re: FPGA package jitter
- From: Tom Sylla <tsylla@xxxxxxxxx>
- To: Alfred Lee <alfred1520@xxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Mon, 21 Sep 2009 14:19:23 -0400
I received lots of off-list replies, so I thought I would try and
answer most of them on-list, as well as answer some of the questions
below:
On Fri, Sep 18, 2009 at 1:44 PM, Alfred Lee <alfred1520@xxxxxxxxx> wrote:
> I have nothing to comment about PDN. I did look at the ML506 quiet and busy
> screen shots. What strikes me with the busy screen shots are the holes
> between the edges, especially near the center of the screen. And also very
> peculiar when considering that the screen shot consists of 1051
> acquisitions, that the last edge on the right is quite clean. In another
> word, when looking at 1/8 the clock frequency, there is very little jitter!
You are seeing the two frequencies line up. In those scope shots, the
core that is running in the Xilinx part is 50MHz and the LVDS clock is
400MHz. The time base is the same for each, so the effects of the
50MHz problem are going to line up with every 8th edge of the 400MHz
clock.
> The waveform suggests unterminated transmission line. Can this or other
> lines see reflections on the chip and count one extra edge?
Usually, we are just driving LVDS or similar signals out to test
points for probing. That is not the normal mode of operation, we are
just doing that for ease of probing. We did probe at the receiver end
on our platform, and the signals have good integrity (besides the
jitter). On the Xilinx reference design, we do not have a receiver, so
the signals are always unterminated.
For the various off-list replies:
It was suggested that we try and look at the frequency component of
the jitter. We did do that early in the debug, and the jitter is just
very clearly at the frequency of the core. I added a couple of scope
screenshots of what we saw:
This is the model in reset:
http://picasaweb.google.com/pastepic/XilinxJitter#5383959835184236098
This is with the model running:
http://picasaweb.google.com/pastepic/XilinxJitter#5383959836042919250
In those shots, we are driving out a single-ended 108MHz clock. In the
first picture, you can see a single, large peak at 108. In the second,
with the model running at 54MHz, you will see the additional peak at
54MHz. As some more background: the core running at ~50MHz is
generated from Xilinx System Generator. We do not control what sort of
activity happens in that core, our customer creates a model using the
Simulink GUI, clicks a button, and the model gets turned into an FPGA
core. In our test cases, we have been running large chains of
multipliers with counters as inputs. The "quiet" core just stops the
counter.
Another suggestion we received was to "split" the core somehow to
spread out the power demands time-wise. This would be fine if was a
fixed core under our own control, but since this is a blob generated
from XSG, we do not have that ability.
One good suggestion we received was to do a spy-hole measurement on
the the I/O rails to see if they are somehow getting the 50MHz noise
coupled on to them. We did measure at back-side vias, and did not see
any ripple induced, but it would be good to check what is happening
inside the device.
There were a few questions about whether it might be related to PLLs
or DCMs. That was our first suspicion too, after checking our power
supplies. We tried designs with just PLLs, just DCMs, mixed PLLs and
DCMs, and also tried different PLL VCO frequencies. The jitter was
present in all cases. The LOCK signal from the PLL is in use, if PLL
lock is lost, the core halts and stays halted, and we do not see that
case. We also did an experiment where we drove the recovered clock out
to an IO. Even that signal showed jitter.
The jitter is not measurably temperature dependent. Cold spray and
heat chamber didn't change anything.
We tried several different I/O standards, LVDS, LVDS_EXT, and HT. The
jitter is present with each, but some do work slightly better than
others, probably because they just end up opening the eye a bit more.
We did check power requirements, and our regulator and layout is
definitely sufficient to handle the load we are putting on the Xilinx
part. This was further proven by using an external bench supply for
the core voltage.
We have Virtex-6 evaluation board on the way. We are hoping that will
behave better. We'll do some measurements on that board as well as
measure the I/O rails and GND driven on I/O signals to see how they
are behaving.
Tom
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