[SI-LIST] Re: FPGA SI Issues in Space Applications

"Well, when I was young..." I landed a position in National
Semiconductor Danbury, CT in 1975 and was transferred to National in
Santa Clara, CA. We were developing Radiation Hardened CMOS memories for
a military application. I was responsible for the Radiation exposure and
testing (which explains the damage), I would take packaged parts, wafers
and die from the Santa Clara facility and drive them over to a Cobalt
reactor somewhere on/near the Moffet AFB campus.  There was a time limit
between removing the wafers from the furnace and the radiation exposure
process, like 15 minutes, I got a few speeding tickets but didn't dare
explain my cargo to the CHP, he just wouldn't understand. The reactor
was a huge Cobalt slab in a 3 story high water tank. The Cobalt slab was
hooked with a long fiberglass rod and slipped into the non-shielded
chute in the exposure room. We would expose the parts to the cobalt
radiation in the shielded room along with Q-Tips for autoclaving,
semi-precious gems (eventually to be precious gems) golf clubs (written
testimony to drive balls further than any other club), and other medical
paraphernalia. I would then rush them back to our lab at National and
perform CV measurements and Memory tests. The test results would be fed
back into the process to perfect the product. Junction depths and doping
are some of the parameters we adjusted to increase radiation hardening.
We also experimented with packaging, ceramic with a hermetically sealed
metal lid was the one which worked best for our product.=20

"Back then I walked to work, up a steep hill - in both directions..."

Straty



-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Sammit Adhya
Sent: Tuesday, April 25, 2006 11:21 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] FPGA SI Issues in Space Applications

Hello All,

This is my first time posting to the list so hopefully the question
isn't too generic. I'm currently working on a research project to use
FPGAs as flight computers in space at the University of Colorado. I was
wondering if people had any general advice for designing circuits in
space with it comes to signal integrity and high radiation environments.

Things like single event upsets have already been addressed, but I was
looking for some insight issues beyond SEUs, SETs and SEEs. Any specific
ways of routing circuits or designing them to inherently protect them
the harsh space environment? Thanks!

--
Sincerely,
Sammit Adhya
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