[SI-LIST] Re: FPGA SI Issues in Space Applications

Just to add to the mix..

The philosophy of designing circuits to withstand partical effects is a 
tricky subject to discuss openly, it may even have restrictions.

Needless to say, considder the effect on a semiconductor when high 
energy particals arrive in the lattice.

The art/science is designing a circuit such that the effects first are 
not catostrophic: second, that over time with irradiation does not 
change the circuit characteristics.

More than this.... you will need more specialised help

Chris Padilla (cpad) wrote on 4/26/2006, 12:59 PM:

 > You are basically asking about immunity requirements for the chips.  To
 > put it simply, you need to protect the ICs by placing them in a sealed
 > metal box.  Naturally, the devil is in the details!!
 >
 > How do you plan to test this product to this environment?  Back in my
 > days at NASA-Ames, we used to take semi-conductor arrays to the
 > cyclotron located at the University of California, Davis, and fire
 > particles at the arrays to simulate sun bursts and cosmic waves and
 > such.=20
 >
 > You can also take such products to any EMC lab and have them do radiated
 > immunity tests.  Basically they just bombard your product with RF energy
 > and see how it performs.
 >
 > Chris Padilla
 > SI Engineer
 > Cisco Systems
 > San Jose, CA
 >
 > -----Original Message-----
 > From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
 > On Behalf Of Sammit Adhya
 > Sent: Wednesday, April 26, 2006 10:42 AM
 > To: si-list@xxxxxxxxxxxxx
 > Subject: [SI-LIST] Re: FPGA SI Issues in Space Applications
 >
 > Our area of research is unique in the sense that we're using SRAM based
 > FPGAs from Xilinx. The idea is that with scrubbing and triple modular
 > redundancy, that should provide immunity for SEUs and latchup's. That
 > has already been done, so we're working on basically the ability to
 > dynamically move around different reconfigurable modules in the case of
 > failures. In theory, until you have hit the device with the maximum
 > ionizing dose, the devices should not fail.
 >
 > I guess I just don't have a good understanding of how SI issues affect
 > signals within the FPGA and what are the common practices used to
 > prevent these issues when writing HDL. The harsh space environment I
 > would think adds to this issues and I haven't seen much on trying to
 > inherently protect the hardware. Thanks!
 >
 > Sincerely,
 > Sammit Adhya
 >
 > On 4/26/06, Tom Biggs <tbiggs@xxxxxxxxxxxxxxxxxxxxx> wrote:
 > > Assuming you are talking about satellites and not launchers, one issue
 >
 > > to consider is that long term radiation affects transister=20
 > > characteristics. So you can't trust specs such as Vil, Vih, Vol,
 > Voh,=20
 > > rise times, propogation delays.
 > >
 > > So how do you design? You understand what the affects are, and you=20
 > > adjust the numbers for the worst case over the lifetime of the=20
 > > satellite. Lots of extra margin in the design is highly recommended.
 > >
 > > I'm glad to see that you've addressed the SEU issue. A flip-flop
 > that=20
 > > decides to change state randomly is difficult to design around. It
 > is=20
 > > even harder when the flip-flop is controlling the configuration of the
 >
 > > FPGA. How are you dealing with radiation induced latch-up?
 > >
 > > Using non-radiation hardened electronics in space is tricky.
 > > There was once a Japanese satellite that used seven microprocessors.=20
 > > The processors were not radiation hardened, but they didn't worry=20
 > > because of all of the redundancy. If one or two get a radiation hit,=20
 > > the others take over and reset the crashed cpus. Then along came a=20
 > > strong solar flare and knocked out all seven at once. End of
 > satellite.
 > >
 > >    -tom
 > >
 > > -----Original Message-----
 > > From: si-list-bounce@xxxxxxxxxxxxx=20
 > > [mailto:si-list-bounce@xxxxxxxxxxxxx]
 > > On Behalf Of Sammit Adhya
 > > Sent: Tuesday, April 25, 2006 11:21 PM
 > > To: si-list@xxxxxxxxxxxxx
 > > Subject: [SI-LIST] FPGA SI Issues in Space Applications
 > >
 > >
 > > Hello All,
 > >
 > > This is my first time posting to the list so hopefully the question=20
 > > isn't too generic. I'm currently working on a research project to
 > use=20
 > > FPGAs as flight computers in space at the University of Colorado. I=20
 > > was wondering if people had any general advice for designing
 > circuits=20
 > > in space with it comes to signal integrity and high radiation
 > environments.
 > >
 > > Things like single event upsets have already been addressed, but I was
 >
 > > looking for some insight issues beyond SEUs, SETs and SEEs. Any=20
 > > specific ways of routing circuits or designing them to inherently=20
 > > protect them the harsh space environment? Thanks!
 > >
 > > --
 > > Sincerely,
 > > Sammit Adhya
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-- 
Cheers,
Derek Walton
L F Research
Poplar Grove, IL 61065, USA

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