[SI-LIST] Re: FPGA SI Issues in Space Applications
- From: "Sammit Adhya" <sammit.adhya@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 26 Apr 2006 11:41:39 -0600
Our area of research is unique in the sense that we're using SRAM
based FPGAs from Xilinx. The idea is that with scrubbing and triple
modular redundancy, that should provide immunity for SEUs and
latchup's. That has already been done, so we're working on basically
the ability to dynamically move around different reconfigurable
modules in the case of failures. In theory, until you have hit the
device with the maximum ionizing dose, the devices should not fail.
I guess I just don't have a good understanding of how SI issues affect
signals within the FPGA and what are the common practices used to
prevent these issues when writing HDL. The harsh space environment I
would think adds to this issues and I haven't seen much on trying to
inherently protect the hardware. Thanks!
Sincerely,
Sammit Adhya
On 4/26/06, Tom Biggs <tbiggs@xxxxxxxxxxxxxxxxxxxxx> wrote:
> Assuming you are talking about satellites and not launchers, one issue
> to consider is that long term radiation affects transister
> characteristics. So you can't trust specs such as Vil, Vih, Vol, Voh,
> rise times, propogation delays.
>
> So how do you design? You understand what the affects are, and you
> adjust the numbers for the worst case over the lifetime of the
> satellite. Lots of extra margin in the design is highly recommended.
>
> I'm glad to see that you've addressed the SEU issue. A flip-flop that
> decides to change state randomly is difficult to design around. It is
> even harder when the flip-flop is controlling the configuration of the
> FPGA. How are you dealing with radiation induced latch-up?
>
> Using non-radiation hardened electronics in space is tricky.
> There was once a Japanese satellite that used seven microprocessors. The
> processors were not radiation hardened, but they didn't worry because of
> all of the redundancy. If one or two get a radiation hit, the others
> take over and reset the crashed cpus. Then along came a strong solar
> flare and knocked out all seven at once. End of satellite.
>
> -tom
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Sammit Adhya
> Sent: Tuesday, April 25, 2006 11:21 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] FPGA SI Issues in Space Applications
>
>
> Hello All,
>
> This is my first time posting to the list so hopefully the question
> isn't too generic. I'm currently working on a research project to use
> FPGAs as flight computers in space at the University of Colorado. I was
> wondering if people had any general advice for designing circuits in
> space with it comes to signal integrity and high radiation environments.
>
> Things like single event upsets have already been addressed, but I was
> looking for some insight issues beyond SEUs, SETs and SEEs. Any specific
> ways of routing circuits or designing them to inherently protect them
> the harsh space environment? Thanks!
>
> --
> Sincerely,
> Sammit Adhya
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- References:
- [SI-LIST] Re: FPGA SI Issues in Space Applications
- From: Tom Biggs
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- » [SI-LIST] Re: FPGA SI Issues in Space Applications
- [SI-LIST] Re: FPGA SI Issues in Space Applications
- From: Tom Biggs