[SI-LIST] Re: FPGA SI Issues in Space Applications

Assuming you are talking about satellites and not launchers, one issue
to consider is that long term radiation affects transister
characteristics. So you can't trust specs such as Vil, Vih, Vol, Voh,
rise times, propogation delays.

So how do you design? You understand what the affects are, and you
adjust the numbers for the worst case over the lifetime of the
satellite. Lots of extra margin in the design is highly recommended.

I'm glad to see that you've addressed the SEU issue. A flip-flop that
decides to change state randomly is difficult to design around. It is
even harder when the flip-flop is controlling the configuration of the
FPGA. How are you dealing with radiation induced latch-up?

Using non-radiation hardened electronics in space is tricky.
There was once a Japanese satellite that used seven microprocessors. The
processors were not radiation hardened, but they didn't worry because of
all of the redundancy. If one or two get a radiation hit, the others
take over and reset the crashed cpus. Then along came a strong solar
flare and knocked out all seven at once. End of satellite.

    -tom

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Sammit Adhya
Sent: Tuesday, April 25, 2006 11:21 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] FPGA SI Issues in Space Applications


Hello All,

This is my first time posting to the list so hopefully the question
isn't too generic. I'm currently working on a research project to use
FPGAs as flight computers in space at the University of Colorado. I was
wondering if people had any general advice for designing circuits in
space with it comes to signal integrity and high radiation environments.

Things like single event upsets have already been addressed, but I was
looking for some insight issues beyond SEUs, SETs and SEEs. Any specific
ways of routing circuits or designing them to inherently protect them
the harsh space environment? Thanks!

--
Sincerely,
Sammit Adhya
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