[SI-LIST] Re: Etch back - plating tail effect
- From: "Ozgur Misman" <omism@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 8 Jan 2002 14:31:55 -0700
Hi Ashley,
Are you sure it is an etchback process? Actually, etchback is a process
designed to remove the plating tails. It could be a spot removal (laser
etchbak) which disconnects the tail from the signal and leaves the rest of
the tail floting or it could be complete removal of the plating tail.
Having said that, I think the most obvious high speed effect you would see
is excessive ringing . It is typically recommended that the electrical
delay of the stub is less than the half risetime(10%-90%). In that case the
stub should act as a capacitive load which may not be as bad as excessive
ringing.
I have put together simulations in the past using Advanced Design System
from Agilent. It is fairly easy using the multilayer interconnect library
and the time domain tools and should help you set a threshold on the
plating tail length for it not to degrade the signal quality.
If it is a laminate package you are considering I recommend you place your
high speed signals along the outer row of the package solder
balls,preferrably at the center. There the tails would be much shorter!.
Hope this helps
Ozgur
"Rebelo, Ashley (Ash)" <arebelo@xxxxxxxxx>@freelists.org on 01/08/2002
02:06:04 PM
Please respond to arebelo@xxxxxxxxx
Sent by: si-list-bounce@xxxxxxxxxxxxx
To: si-list@xxxxxxxxxxxxx
cc:
Subject: [SI-LIST] Etch back - plating tail effect
Hi all,
I have question in regards to the plating tail on a signal trace that is
left after etch back: What is the minimum length for this tail that would
cause a signal integrity problem (antenna effect)? I am concerned because
it's a high speed application.
Thanks for the help,
ASHLEY
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