[SI-LIST] Errata for "Timing Analysis for Signal Integrity Engineers"

1. Page 17.  On the second rising edge of the clock in Figure 2.3, the Q 
output should stay high.
2. Page 150.  "...the DRAM setup and hold specifications (tDS and tDH) 
already account for the method used to measure threshold crossings..."

This is incorrect.  I started my DDR2 budget with a 1500 ps bit time, took 
out the silicon, and then accounted for various interconnect effects.  My 
mistake was including the effects of memory controller output edge rate 
degradation with the silicon.  It really should be part of the 
interconnect.  This only affected the write budget, which had plenty of 
margin to absorb the mistake in the example.  The read budget is usually 
more stressed in my experience.

If you made a similar assumption in your DDR2 budget, there are two things 
in your favor.  First, I used the full range of the DRAM output slew rate 
spec.  I would expect to see a tighter spec on a memory controller ASIC. 
Second, the DRAM input threshold specs are much wider than what you would 
see if you did a simple unity gain point analysis of the receiver circuit 
(see Figure 3.2).  The only reason I can come up with for this is that the 
DRAM input threshold specs account for Vref ac noise and dc shift, but 
I've never gotten to the bottom of this.  I included Vref in the 
interconnect budget just to be safe.

The bottom line:  I think your hardware will run fine even if you made the 
same mistake I did.

3. Page 220.  Equation B.4 needs a mu-naught-J term.  Leave it to a 
physics major to botch Maxwell's equations!  Colin will never let me 
forget.  :-)

Truth be told, items 1 and 3 were correct in the rough draft.  It's 
amazing how many times you can read something and still miss the mistake. 
Bernard warned me this would happen.  We fixed the mistakes in "A Signal 
Integrity Engineer's Companion."

I hope this didn't cause anyone too much trouble.  I'd be glad to discuss 
by email.  Thanks to everyone who provided feedback on the book.

Greg Edlund
Senior Engineer
Signal Integrity and System Timing
IBM Systems & Technology Group
3605 Hwy. 52 N  Bldg 050-2
Rochester, MN 55901



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