[SI-LIST] Re: Embedded Passives

The Ohmega-Ply is a thin-film process hence you can ignore the
transition from copper to material but . . . things you will need to do
for proper trace extraction with your SI tool. You must represent the
area of the board that the resistor will occupy as a resistor on the
schematic and give it a footprint name, and create a footprint for it.
That way you can extract the topology of the net for simulation. Your
simulator is probably NOT a three D field solver. The model you assign
to the resistor will have some stray capacitance, however small, to the
next planes up and down which should be represented in the RLGC model
you assign. Ohmega-Ply should have some experience with the RLGC factors
of their thin-film resistors. They list their inductance at less than
0.6nh so use this for the L in the RLGC model. C will vary as the
dielectric constant of your laminate and the laminate thickness.

Lastly, when you build you coupons for the prototypes, put some the R's
for each type of R and for each layers in the test coupons. Layout the
coupons to accommodate SMA surface mount connectors so, if necessary,
you can QA the thin -film process and or measure the actual RLGC
response of your buried passives on a Network analyzer to confirm
engineering values as sanity check.

Typically, these type of passives are used on stripline signal layers.

Steven Salkow
Lockheed IS&GS
3130 Zanker Rd, San Jose
Ca. 95134
W:(408) 473-4058
H:(925) 462-1075
steven.salkow@xxxxxxxx




-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Tate, David
Sent: Wednesday, July 25, 2007 6:24 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Embedded Passives

Are there any pitfalls in performing SI analysis when using embedded
passives?
 
Modeling the plane capacitances looks straight forward - distance
between the planes, the dielectric constant, tangent loss etc... should
be all I need.
 
We are looking at products like Ohmega-Ply to provide embedded
resistors. How do I model the transition from the copper trace to the
resistive material, or can I ignore this transition region?
 
best regards,
 
David Tate
Lockheed Martin Missiles and Fire Control
Senior Staff Circuit Design Engineer
Electrical Engineering - FPGA/Processor Design
E-Mail: david.tate@xxxxxxxx <mailto:david.tate@xxxxxxxx>

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: