[SI-LIST] Embedded Passives

Are there any pitfalls in performing SI analysis when using embedded
passives?
 
Modeling the plane capacitances looks straight forward - distance
between the planes, the dielectric constant, tangent loss etc... should
be all I need.
 
We are looking at products like Ohmega-Ply to provide embedded
resistors. How do I model the transition from the copper trace to the
resistive material, or can I ignore this transition region?
 
best regards,
 
David Tate
Lockheed Martin Missiles and Fire Control
Senior Staff Circuit Design Engineer
Electrical Engineering - FPGA/Processor Design
E-Mail: david.tate@xxxxxxxx <mailto:david.tate@xxxxxxxx>

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