[SI-LIST] Re: Effect of Split Planes on Single Stripline Signals
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Walter <waltinaustin@xxxxxxxxx>
- Date: Wed, 09 Jun 2010 16:09:41 -0700
If you really want to know push it through a field solver. You could
download the trial of Simbeor. If the exercise proves valuable as it
should then you can use that to help justify purchasing a copy.
That said, the slot is going to present a modest impedance discontinuity
to signals passing on the far strip line layer, and a large
discontinuity to the near layer. The split plane layer is coupling
somewhere in the neighborhood of 5% of the DDR3 signals from the far
strip line. How much gets on particular signal on the near strip lines
depends on geometry of the polygons and strip lines, and bypass of the
polygons. The other concern is that if the splits extend to the edge of
the PCB, then you have a location that is a potential emitter. You can
mitigate that somewhat with bypass caps between polygons near the edge
of the PCB in addition to bypass from near the signal crossings.
Steve.
Walter wrote:
> I have an application were I am contemplating routing signals across splits
> in a plane. Everyone know that this is a big no no for high speed signals.
> But in this case, it's a asymmetric single stripline. The traces are 12 mils
> from a split plane and 3mils from a solid plane. Can I expect a measurable
> effect on my DDR3 1600 signals? I would like to simulate this with a 3d
> solver but I don't have access to one.
>
> Regards,
> Walter Haskell
> Polycom. Inc.
>
>
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--
Steve Weir
IPBLOX, LLC
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